csc_top.v

color space convert verilog

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    14:23:05 11/29/06
// Design Name:    
// Module Name:    csc_top
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module csc_top(X, Y, Z, Clock, Reset, R, G, B);

  parameter TOP_OUT_SIZE  =  12; // uncomment to get  12-bit input & output...

  input  Clock; 
  input  Reset;
  input  [(TOP_OUT_SIZE - 1):0] X; 
  input  [(TOP_OUT_SIZE - 1):0] Y; 
  input  [(TOP_OUT_SIZE - 1):0] Z; 
  output [(TOP_OUT_SIZE - 1):0] R; 
  output [(TOP_OUT_SIZE - 1):0] G; 
  output [(TOP_OUT_SIZE - 1):0] B; 

  reg [(TOP_OUT_SIZE - 1):0] R;
  reg [(TOP_OUT_SIZE - 1):0] G;
  reg [(TOP_OUT_SIZE - 1):0] B;

  // Define internal signals
  reg [(TOP_OUT_SIZE - 1):0] X_In; 
  reg [(TOP_OUT_SIZE - 1):0] Y_In; 
  reg [(TOP_OUT_SIZE - 1):0] Z_In;

  wire [(TOP_OUT_SIZE - 1):0] R_sig; 
  wire [(TOP_OUT_SIZE - 1):0] G_sig; 
  wire [(TOP_OUT_SIZE - 1):0] B_sig; 
	
  // Input registers (should be pushed into IOBs)
  always @(posedge Clock or negedge Reset)
  begin : In_Reg
  	if(!Reset)
		begin
			X_In <= 12'b0001_0000_0000;
			Z_In <= 12'b0001_0000_0000;
			Y_In <= 12'b0001_0000_0000;
		end
		else
		begin
		  X_In <= X; 
		  Y_In <= Y; 
		  Z_In <= Z; 
		end
  end 

  // Output registers (should be pushed into IOBs)
  always @(posedge Clock or negedge Reset)
  begin : Out_Reg
    if(!Reset)
	  begin
		 	R <= 12'b0001_0000_0000;
			G <= 12'b0001_0000_0000;
			B <= 12'b0001_0000_0000;
	  end
	  else
	  begin
	 	  R <= R_sig ; 
      G <= G_sig ; 
      B <= B_sig ; 
	  end
  end 


  // CSC instantiation
  csc  #(TOP_OUT_SIZE) CSC_module
  (
    .Clock(Clock),
	 .Reset(Reset),
    .X(X_In),
    .Y(Y_In),
    .Z(Z_In),
    .R(R_sig),
    .G(G_sig),
    .B(B_sig)
  );

endmodule