ad_conv.vhd

利用CPLD来控制AD进行电压采样

-- tlc0820ac ---a/d转换
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ad_conv is
port(clk :in std_logic;--输入时钟信号50MHz
	 rst : in std_logic;  --复位
	 cs : out std_logic;
	 rd : out std_logic;
	 int : in std_logic;
	 datain : in std_logic_vector(7 downto 0);
	ld: out std_logic_vector(7 downto 0)
	);
end ad_conv;
architecture aa of ad_conv is
	signal t_rd, t_cs : std_logic;
	signal count: integer range 0 to 4999;	 --total采样间隔为10ns*5000=100us
	signal t_int: integer range 0 to 15;		--320ns 肯定够int变为高了
	signal t_data :std_logic_vector(7 downto 0);

begin
process(clk,int,rst)
begin

--异步复位
if rst='1' then
	count <= 0;
	t_cs <= '1';
	t_rd <= '1';
	t_data <= "00000000";

--计数器
	elsif(clk'event and clk='1') then
		if count=4999 then
			count<=0;
		else 
			count<=count+1;
		end if;

		--时序控制
		if count < 3 then
			t_cs<='1';
			t_rd<='1';
		elsif count < 23 then
			t_cs<='0';
			t_rd<='1';
		else
			t_cs<='0';
			t_rd<='0';
			if int='0' then
				t_int<=t_int+1;
			else
				t_int<=0;
			end if;
			if t_int = 2 then
				t_data <= datain;
			end if;
		end if;
end if;
end process;
	cs<=t_cs;
	rd<=t_rd;
	ld <= t_data;
end aa;