prev_cmp_char_7seg.map.qmsg

lab1 report, with codelab1 report, with code

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.1 Build 163 10/28/2008 SJ Web Edition " "Info: Version 8.1 Build 163 10/28/2008 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 18 23:21:12 2009 " "Info: Processing started: Wed Mar 18 23:21:12 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off char_7seg -c char_7seg " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off char_7seg -c char_7seg" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "char_7seg.vhd 4 2 " "Info: Found 4 design units, including 2 entities, in source file char_7seg.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 char_7seg-behavioral " "Info: Found design unit 1: char_7seg-behavioral" {  } { { "char_7seg.vhd" "" { Text "S:/dda/lab1/char_7seg.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 MUX3_1-behavior " "Info: Found design unit 2: MUX3_1-behavior" {  } { { "char_7seg.vhd" "" { Text "S:/dda/lab1/char_7seg.vhd" 39 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 char_7seg " "Info: Found entity 1: char_7seg" {  } { { "char_7seg.vhd" "" { Text "S:/dda/lab1/char_7seg.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "2 MUX3_1 " "Info: Found entity 2: MUX3_1" {  } { { "char_7seg.vhd" "" { Text "S:/dda/lab1/char_7seg.vhd" 32 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "SW char_7seg.vhd(14) " "Error (10482): VHDL error at char_7seg.vhd(14): object \"SW\" is used but not declared" {  } { { "char_7seg.vhd" "" { Text "S:/dda/lab1/char_7seg.vhd" 14 0 0 } }  } 0 10482 "VHDL error at %2!s!: object \"%1!s!\" is used but not declared" 0 0 "" 0 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "SW char_7seg.vhd(12) " "Error (10482): VHDL error at char_7seg.vhd(12): object \"SW\" is used but not declared" {  } { { "char_7seg.vhd" "" { Text "S:/dda/lab1/char_7seg.vhd" 12 0 0 } }  } 0 10482 "VHDL error at %2!s!: object \"%1!s!\" is used but not declared" 0 0 "" 0 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 2 s 0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 0 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "214 " "Error: Peak virtual memory: 214 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Error" "EQEXE_END_BANNER_TIME" "Wed Mar 18 23:21:13 2009 " "Error: Processing ended: Wed Mar 18 23:21:13 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:01 " "Error: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Error: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}