char_7seg.vhd

来自「lab1 report, with codelab1 report, with 」· VHDL 代码 · 共 29 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL, IEEE.NUMERIC_STD.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity char_7seg is
    Port ( SW : in std_logic_vector (0 to 1);
           hex00 : out std_logic_vector( 0 to 6));
end char_7seg;
architecture behavioral of char_7seg is
begin
--part 1
process (SW)
begin
   case SW is
when "00" => hex00 <= "1000010"; --d
when "01" => hex00 <= "0110000"; --E
when "10" => hex00 <= "1001111"; --1
when "11" => hex00 <= "1111111";--None
--when 4 => hex0 <= "00010000";
--when 5 => hex0 <= "00100000";
--when 6 => hex0 <= "01000000";
--when 7 => hex0 <= "10000000";
end case;

end process;
end behavioral;