char_7seg.fit.rpt

lab1 report, with codelab1 report, with code

Fitter report for char_7seg
Wed Mar 18 23:23:07 2009
Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Incremental Compilation Preservation Summary
  5. Incremental Compilation Partition Settings
  6. Incremental Compilation Placement Preservation
  7. Pin-Out File
  8. Fitter Resource Usage Summary
  9. Input Pins
 10. Output Pins
 11. I/O Bank Usage
 12. All Package Pins
 13. Output Pin Default Load For Reported TCO
 14. Fitter Resource Utilization by Entity
 15. Delay Chain Summary
 16. Pad To Core Delay Chain Fanout
 17. Non-Global High Fan-Out Signals
 18. Interconnect Usage Summary
 19. LAB Logic Elements
 20. LAB Signals Sourced
 21. LAB Signals Sourced Out
 22. LAB Distinct Inputs
 23. Fitter Device Options
 24. Operating Settings and Conditions
 25. Estimated Delay Added for Hold Timing
 26. Fitter Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------------+
; Fitter Summary                                                               ;
+------------------------------------+-----------------------------------------+
; Fitter Status                      ; Successful - Wed Mar 18 23:23:07 2009   ;
; Quartus II Version                 ; 8.1 Build 163 10/28/2008 SJ Web Edition ;
; Revision Name                      ; char_7seg                               ;
; Top-level Entity Name              ; char_7seg                               ;
; Family                             ; Cyclone II                              ;
; Device                             ; EP2C20F484C7                            ;
; Timing Models                      ; Final                                   ;
; Total logic elements               ; 1 / 18,752 ( < 1 % )                    ;
;     Total combinational functions  ; 1 / 18,752 ( < 1 % )                    ;
;     Dedicated logic registers      ; 0 / 18,752 ( 0 % )                      ;
; Total registers                    ; 0                                       ;
; Total pins                         ; 9 / 315 ( 3 % )                         ;
; Total virtual pins                 ; 0                                       ;
; Total memory bits                  ; 0 / 239,616 ( 0 % )                     ;
; Embedded Multiplier 9-bit elements ; 0 / 52 ( 0 % )                          ;
; Total PLLs                         ; 0 / 4 ( 0 % )                           ;
+------------------------------------+-----------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                                      ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+
; Option                                                             ; Setting                        ; Default Value                  ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+
; Device                                                             ; EP2C20F484C7                   ;                                ;
; Minimum Core Junction Temperature                                  ; 0                              ;                                ;
; Maximum Core Junction Temperature                                  ; 85                             ;                                ;
; Fit Attempts to Skip                                               ; 0                              ; 0.0                            ;
; Use smart compilation                                              ; Off                            ; Off                            ;
; Use TimeQuest Timing Analyzer                                      ; Off                            ; Off                            ;
; Router Timing Optimization Level                                   ; Normal                         ; Normal                         ;
; Placement Effort Multiplier                                        ; 1.0                            ; 1.0                            ;
; Router Effort Multiplier                                           ; 1.0                            ; 1.0                            ;
; Always Enable Input Buffers                                        ; Off                            ; Off                            ;
; Optimize Hold Timing                                               ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Multi-Corner Timing                                       ; Off                            ; Off                            ;
; PowerPlay Power Optimization                                       ; Normal compilation             ; Normal compilation             ;
; Optimize Timing                                                    ; Normal compilation             ; Normal compilation             ;
; Optimize Timing for ECOs                                           ; Off                            ; Off                            ;
; Regenerate full fit report during ECO compiles                     ; Off                            ; Off                            ;
; Optimize IOC Register Placement for Timing                         ; On                             ; On                             ;
; Limit to One Fitting Attempt                                       ; Off                            ; Off                            ;
; Final Placement Optimizations                                      ; Automatically                  ; Automatically                  ;