char_7seg.tan.rpt

lab1 report, with codelab1 report, with code

Classic Timing Analyzer report for char_7seg
Wed Mar 18 23:23:11 2009
Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. tpd
  5. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                      ;
+------------------------------+-------+---------------+-------------+-------+----------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time ; From  ; To       ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+-------+----------+------------+----------+--------------+
; Worst-case tpd               ; N/A   ; None          ; 5.740 ns    ; SW[0] ; hex00[5] ; --         ; --       ; 0            ;
; Total number of failed paths ;       ;               ;             ;       ;          ;            ;          ; 0            ;
+------------------------------+-------+---------------+-------------+-------+----------+------------+----------+--------------+


+--------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                           ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                              ; Setting            ; From ; To ; Entity Name ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                         ; EP2C20F484C7       ;      ;    ;             ;
; Timing Models                                                       ; Final              ;      ;    ;             ;
; Default hold multicycle                                             ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                           ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                              ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                      ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                                    ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                               ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                             ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                                    ; Off                ;      ;    ;             ;
; Enable Clock Latency                                                ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                       ; Off                ;      ;    ;             ;
; Minimum Core Junction Temperature                                   ; 0                  ;      ;    ;             ;
; Maximum Core Junction Temperature                                   ; 85                 ;      ;    ;             ;
; Number of source nodes to report per destination node               ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                               ; 10                 ;      ;    ;             ;
; Number of paths to report                                           ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                        ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                              ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                          ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                        ; On                 ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis      ; Off                ;      ;    ;             ;
; Removes common clock path pessimism (CCPP) during slack computation ; Off                ;      ;    ;             ;
; Output I/O Timing Endpoint                                          ; Near End           ;      ;    ;             ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+


+----------------------------------------------------------------+
; tpd                                                            ;
+-------+-------------------+-----------------+-------+----------+
; Slack ; Required P2P Time ; Actual P2P Time ; From  ; To       ;
+-------+-------------------+-----------------+-------+----------+
; N/A   ; None              ; 5.740 ns        ; SW[0] ; hex00[5] ;
; N/A   ; None              ; 5.710 ns        ; SW[0] ; hex00[0] ;
; N/A   ; None              ; 5.337 ns        ; SW[1] ; hex00[5] ;
; N/A   ; None              ; 5.307 ns        ; SW[1] ; hex00[0] ;
; N/A   ; None              ; 5.011 ns        ; SW[1] ; hex00[1] ;
; N/A   ; None              ; 4.645 ns        ; SW[1] ; hex00[2] ;
; N/A   ; None              ; 4.627 ns        ; SW[0] ; hex00[6] ;
; N/A   ; None              ; 4.624 ns        ; SW[0] ; hex00[4] ;
; N/A   ; None              ; 4.617 ns        ; SW[0] ; hex00[3] ;
+-------+-------------------+-----------------+-------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 8.1 Build 163 10/28/2008 SJ Web Edition
    Info: Processing started: Wed Mar 18 23:23:11 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off char_7seg -c char_7seg --timing_analysis_only
Info: Longest tpd from source pin "SW[0]" to destination pin "hex00[5]" is 5.740 ns
    Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L22; Fanout = 4; PIN Node = 'SW[0]'
    Info: 2: + IC(0.808 ns) + CELL(0.545 ns) = 2.379 ns; Loc. = LCCOMB_X49_Y15_N0; Fanout = 2; COMB Node = 'Mux1~21'
    Info: 3: + IC(0.521 ns) + CELL(2.840 ns) = 5.740 ns; Loc. = PIN_K22; Fanout = 0; PIN Node = 'hex00[5]'
    Info: Total cell delay = 4.411 ns ( 76.85 % )
    Info: Total interconnect delay = 1.329 ns ( 23.15 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 161 megabytes
    Info: Processing ended: Wed Mar 18 23:23:12 2009
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:00