char_7seg.vhd.bak

lab1 report, with codelab1 report, with code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL, IEEE.NUMERIC_STD.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity char_7seg is
    Port ( SW : in std_logic_vector (0 to 1);
           hex00 : out std_logic_vector( 0 to 6));
end char_7seg;
architecture behavioral of char_7seg is
begin
--part 1
process (SW)
begin
   case SW is
when "00" => hex00 <= "1000010"; --d
when "01" => hex00 <= "0110000"; --E
when "10" => hex00 <= "1001111"; --1
when "11" => hex00 <= "1111111";--None
--when 4 => hex0 <= "00010000";
--when 5 => hex0 <= "00100000";
--when 6 => hex0 <= "01000000";
--when 7 => hex0 <= "10000000";
end case;

end process;
end behavioral;

--part 2 2-bit wide 3:1 multiplexer
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity MUX3_1 is  
port (
      se1     :in std_logic_vector (1 downto 0);
      U,V,W   :in std_logic;
      M       :out std_logic
      );
  end MUX3_1;
architecture behavior of MUX3_1 is 
begin
-- if statements
    process (Se1,U,V,W)
    begin
    if (Se1 = "00") then
     M<=U;
     Elsif (Se1 = "01") then 
     M<=V; 
     Elsif (Se1 = "10") then 
     M<=W;
    end if;
   end process;
  end behavior;