ram.hier_info

ram的vhdl源代码在colloy实现

address_a[5] => ram_block2a1.PORTAADDR5
address_a[5] => ram_block2a2.PORTAADDR5
address_a[5] => ram_block2a3.PORTAADDR5
address_a[5] => ram_block2a4.PORTAADDR5
address_a[5] => ram_block2a5.PORTAADDR5
address_a[5] => ram_block2a6.PORTAADDR5
address_a[5] => ram_block2a7.PORTAADDR5
address_a[5] => ram_block2a8.PORTAADDR5
address_a[5] => ram_block2a9.PORTAADDR5
address_a[5] => ram_block2a10.PORTAADDR5
address_a[5] => ram_block2a11.PORTAADDR5
address_a[5] => ram_block2a12.PORTAADDR5
address_a[5] => ram_block2a13.PORTAADDR5
address_a[5] => ram_block2a14.PORTAADDR5
address_a[5] => ram_block2a15.PORTAADDR5
address_a[6] => ram_block2a0.PORTAADDR6
address_a[6] => ram_block2a1.PORTAADDR6
address_a[6] => ram_block2a2.PORTAADDR6
address_a[6] => ram_block2a3.PORTAADDR6
address_a[6] => ram_block2a4.PORTAADDR6
address_a[6] => ram_block2a5.PORTAADDR6
address_a[6] => ram_block2a6.PORTAADDR6
address_a[6] => ram_block2a7.PORTAADDR6
address_a[6] => ram_block2a8.PORTAADDR6
address_a[6] => ram_block2a9.PORTAADDR6
address_a[6] => ram_block2a10.PORTAADDR6
address_a[6] => ram_block2a11.PORTAADDR6
address_a[6] => ram_block2a12.PORTAADDR6
address_a[6] => ram_block2a13.PORTAADDR6
address_a[6] => ram_block2a14.PORTAADDR6
address_a[6] => ram_block2a15.PORTAADDR6
address_a[7] => ram_block2a0.PORTAADDR7
address_a[7] => ram_block2a1.PORTAADDR7
address_a[7] => ram_block2a2.PORTAADDR7
address_a[7] => ram_block2a3.PORTAADDR7
address_a[7] => ram_block2a4.PORTAADDR7
address_a[7] => ram_block2a5.PORTAADDR7
address_a[7] => ram_block2a6.PORTAADDR7
address_a[7] => ram_block2a7.PORTAADDR7
address_a[7] => ram_block2a8.PORTAADDR7
address_a[7] => ram_block2a9.PORTAADDR7
address_a[7] => ram_block2a10.PORTAADDR7
address_a[7] => ram_block2a11.PORTAADDR7
address_a[7] => ram_block2a12.PORTAADDR7
address_a[7] => ram_block2a13.PORTAADDR7
address_a[7] => ram_block2a14.PORTAADDR7
address_a[7] => ram_block2a15.PORTAADDR7
address_b[0] => ram_block2a0.PORTBADDR
address_b[0] => ram_block2a1.PORTBADDR
address_b[0] => ram_block2a2.PORTBADDR
address_b[0] => ram_block2a3.PORTBADDR
address_b[0] => ram_block2a4.PORTBADDR
address_b[0] => ram_block2a5.PORTBADDR
address_b[0] => ram_block2a6.PORTBADDR
address_b[0] => ram_block2a7.PORTBADDR
address_b[0] => ram_block2a8.PORTBADDR
address_b[0] => ram_block2a9.PORTBADDR
address_b[0] => ram_block2a10.PORTBADDR
address_b[0] => ram_block2a11.PORTBADDR
address_b[0] => ram_block2a12.PORTBADDR
address_b[0] => ram_block2a13.PORTBADDR
address_b[0] => ram_block2a14.PORTBADDR
address_b[0] => ram_block2a15.PORTBADDR
address_b[1] => ram_block2a0.PORTBADDR1
address_b[1] => ram_block2a1.PORTBADDR1
address_b[1] => ram_block2a2.PORTBADDR1
address_b[1] => ram_block2a3.PORTBADDR1
address_b[1] => ram_block2a4.PORTBADDR1
address_b[1] => ram_block2a5.PORTBADDR1
address_b[1] => ram_block2a6.PORTBADDR1
address_b[1] => ram_block2a7.PORTBADDR1
address_b[1] => ram_block2a8.PORTBADDR1
address_b[1] => ram_block2a9.PORTBADDR1
address_b[1] => ram_block2a10.PORTBADDR1
address_b[1] => ram_block2a11.PORTBADDR1
address_b[1] => ram_block2a12.PORTBADDR1
address_b[1] => ram_block2a13.PORTBADDR1
address_b[1] => ram_block2a14.PORTBADDR1
address_b[1] => ram_block2a15.PORTBADDR1
address_b[2] => ram_block2a0.PORTBADDR2
address_b[2] => ram_block2a1.PORTBADDR2
address_b[2] => ram_block2a2.PORTBADDR2
address_b[2] => ram_block2a3.PORTBADDR2
address_b[2] => ram_block2a4.PORTBADDR2
address_b[2] => ram_block2a5.PORTBADDR2
address_b[2] => ram_block2a6.PORTBADDR2
address_b[2] => ram_block2a7.PORTBADDR2
address_b[2] => ram_block2a8.PORTBADDR2
address_b[2] => ram_block2a9.PORTBADDR2
address_b[2] => ram_block2a10.PORTBADDR2
address_b[2] => ram_block2a11.PORTBADDR2
address_b[2] => ram_block2a12.PORTBADDR2
address_b[2] => ram_block2a13.PORTBADDR2
address_b[2] => ram_block2a14.PORTBADDR2
address_b[2] => ram_block2a15.PORTBADDR2
address_b[3] => ram_block2a0.PORTBADDR3
address_b[3] => ram_block2a1.PORTBADDR3
address_b[3] => ram_block2a2.PORTBADDR3
address_b[3] => ram_block2a3.PORTBADDR3
address_b[3] => ram_block2a4.PORTBADDR3
address_b[3] => ram_block2a5.PORTBADDR3
address_b[3] => ram_block2a6.PORTBADDR3
address_b[3] => ram_block2a7.PORTBADDR3
address_b[3] => ram_block2a8.PORTBADDR3
address_b[3] => ram_block2a9.PORTBADDR3
address_b[3] => ram_block2a10.PORTBADDR3
address_b[3] => ram_block2a11.PORTBADDR3
address_b[3] => ram_block2a12.PORTBADDR3
address_b[3] => ram_block2a13.PORTBADDR3
address_b[3] => ram_block2a14.PORTBADDR3
address_b[3] => ram_block2a15.PORTBADDR3
address_b[4] => ram_block2a0.PORTBADDR4
address_b[4] => ram_block2a1.PORTBADDR4
address_b[4] => ram_block2a2.PORTBADDR4
address_b[4] => ram_block2a3.PORTBADDR4
address_b[4] => ram_block2a4.PORTBADDR4
address_b[4] => ram_block2a5.PORTBADDR4
address_b[4] => ram_block2a6.PORTBADDR4
address_b[4] => ram_block2a7.PORTBADDR4
address_b[4] => ram_block2a8.PORTBADDR4
address_b[4] => ram_block2a9.PORTBADDR4
address_b[4] => ram_block2a10.PORTBADDR4
address_b[4] => ram_block2a11.PORTBADDR4
address_b[4] => ram_block2a12.PORTBADDR4
address_b[4] => ram_block2a13.PORTBADDR4
address_b[4] => ram_block2a14.PORTBADDR4
address_b[4] => ram_block2a15.PORTBADDR4
address_b[5] => ram_block2a0.PORTBADDR5
address_b[5] => ram_block2a1.PORTBADDR5
address_b[5] => ram_block2a2.PORTBADDR5
address_b[5] => ram_block2a3.PORTBADDR5
address_b[5] => ram_block2a4.PORTBADDR5
address_b[5] => ram_block2a5.PORTBADDR5
address_b[5] => ram_block2a6.PORTBADDR5
address_b[5] => ram_block2a7.PORTBADDR5
address_b[5] => ram_block2a8.PORTBADDR5
address_b[5] => ram_block2a9.PORTBADDR5
address_b[5] => ram_block2a10.PORTBADDR5
address_b[5] => ram_block2a11.PORTBADDR5
address_b[5] => ram_block2a12.PORTBADDR5
address_b[5] => ram_block2a13.PORTBADDR5
address_b[5] => ram_block2a14.PORTBADDR5
address_b[5] => ram_block2a15.PORTBADDR5
address_b[6] => ram_block2a0.PORTBADDR6
address_b[6] => ram_block2a1.PORTBADDR6
address_b[6] => ram_block2a2.PORTBADDR6
address_b[6] => ram_block2a3.PORTBADDR6
address_b[6] => ram_block2a4.PORTBADDR6
address_b[6] => ram_block2a5.PORTBADDR6
address_b[6] => ram_block2a6.PORTBADDR6
address_b[6] => ram_block2a7.PORTBADDR6
address_b[6] => ram_block2a8.PORTBADDR6
address_b[6] => ram_block2a9.PORTBADDR6
address_b[6] => ram_block2a10.PORTBADDR6
address_b[6] => ram_block2a11.PORTBADDR6
address_b[6] => ram_block2a12.PORTBADDR6
address_b[6] => ram_block2a13.PORTBADDR6
address_b[6] => ram_block2a14.PORTBADDR6
address_b[6] => ram_block2a15.PORTBADDR6
address_b[7] => ram_block2a0.PORTBADDR7
address_b[7] => ram_block2a1.PORTBADDR7
address_b[7] => ram_block2a2.PORTBADDR7
address_b[7] => ram_block2a3.PORTBADDR7
address_b[7] => ram_block2a4.PORTBADDR7
address_b[7] => ram_block2a5.PORTBADDR7
address_b[7] => ram_block2a6.PORTBADDR7
address_b[7] => ram_block2a7.PORTBADDR7
address_b[7] => ram_block2a8.PORTBADDR7
address_b[7] => ram_block2a9.PORTBADDR7
address_b[7] => ram_block2a10.PORTBADDR7
address_b[7] => ram_block2a11.PORTBADDR7
address_b[7] => ram_block2a12.PORTBADDR7
address_b[7] => ram_block2a13.PORTBADDR7
address_b[7] => ram_block2a14.PORTBADDR7
address_b[7] => ram_block2a15.PORTBADDR7
clock0 => ram_block2a0.CLK0
clock0 => ram_block2a1.CLK0
clock0 => ram_block2a2.CLK0
clock0 => ram_block2a3.CLK0
clock0 => ram_block2a4.CLK0
clock0 => ram_block2a5.CLK0
clock0 => ram_block2a6.CLK0
clock0 => ram_block2a7.CLK0
clock0 => ram_block2a8.CLK0
clock0 => ram_block2a9.CLK0
clock0 => ram_block2a10.CLK0
clock0 => ram_block2a11.CLK0
clock0 => ram_block2a12.CLK0
clock0 => ram_block2a13.CLK0
clock0 => ram_block2a14.CLK0
clock0 => ram_block2a15.CLK0
clock1 => ram_block2a0.CLK1
clock1 => ram_block2a1.CLK1
clock1 => ram_block2a2.CLK1
clock1 => ram_block2a3.CLK1
clock1 => ram_block2a4.CLK1
clock1 => ram_block2a5.CLK1
clock1 => ram_block2a6.CLK1
clock1 => ram_block2a7.CLK1
clock1 => ram_block2a8.CLK1
clock1 => ram_block2a9.CLK1
clock1 => ram_block2a10.CLK1
clock1 => ram_block2a11.CLK1
clock1 => ram_block2a12.CLK1
clock1 => ram_block2a13.CLK1
clock1 => ram_block2a14.CLK1
clock1 => ram_block2a15.CLK1
clocken1 => ram_block2a0.ENA1
clocken1 => ram_block2a1.ENA1
clocken1 => ram_block2a2.ENA1
clocken1 => ram_block2a3.ENA1
clocken1 => ram_block2a4.ENA1
clocken1 => ram_block2a5.ENA1
clocken1 => ram_block2a6.ENA1
clocken1 => ram_block2a7.ENA1
clocken1 => ram_block2a8.ENA1
clocken1 => ram_block2a9.ENA1
clocken1 => ram_block2a10.ENA1
clocken1 => ram_block2a11.ENA1
clocken1 => ram_block2a12.ENA1
clocken1 => ram_block2a13.ENA1
clocken1 => ram_block2a14.ENA1
clocken1 => ram_block2a15.ENA1
data_a[0] => ram_block2a0.PORTADATAIN
data_a[1] => ram_block2a1.PORTADATAIN
data_a[2] => ram_block2a2.PORTADATAIN
data_a[3] => ram_block2a3.PORTADATAIN
data_a[4] => ram_block2a4.PORTADATAIN
data_a[5] => ram_block2a5.PORTADATAIN
data_a[6] => ram_block2a6.PORTADATAIN
data_a[7] => ram_block2a7.PORTADATAIN
data_a[8] => ram_block2a8.PORTADATAIN
data_a[9] => ram_block2a9.PORTADATAIN
data_a[10] => ram_block2a10.PORTADATAIN
data_a[11] => ram_block2a11.PORTADATAIN
data_a[12] => ram_block2a12.PORTADATAIN
data_a[13] => ram_block2a13.PORTADATAIN
data_a[14] => ram_block2a14.PORTADATAIN
data_a[15] => ram_block2a15.PORTADATAIN
data_b[0] => ram_block2a0.PORTBDATAIN
data_b[1] => ram_block2a1.PORTBDATAIN
data_b[2] => ram_block2a2.PORTBDATAIN
data_b[3] => ram_block2a3.PORTBDATAIN
data_b[4] => ram_block2a4.PORTBDATAIN
data_b[5] => ram_block2a5.PORTBDATAIN
data_b[6] => ram_block2a6.PORTBDATAIN
data_b[7] => ram_block2a7.PORTBDATAIN
data_b[8] => ram_block2a8.PORTBDATAIN
data_b[9] => ram_block2a9.PORTBDATAIN
data_b[10] => ram_block2a10.PORTBDATAIN
data_b[11] => ram_block2a11.PORTBDATAIN
data_b[12] => ram_block2a12.PORTBDATAIN
data_b[13] => ram_block2a13.PORTBDATAIN
data_b[14] => ram_block2a14.PORTBDATAIN
data_b[15] => ram_block2a15.PORTBDATAIN
q_a[0] <= ram_block2a0.PORTADATAOUT
q_a[1] <= ram_block2a1.PORTADATAOUT
q_a[2] <= ram_block2a2.PORTADATAOUT
q_a[3] <= ram_block2a3.PORTADATAOUT
q_a[4] <= ram_block2a4.PORTADATAOUT
q_a[5] <= ram_block2a5.PORTADATAOUT
q_a[6] <= ram_block2a6.PORTADATAOUT
q_a[7] <= ram_block2a7.PORTADATAOUT
q_a[8] <= ram_block2a8.PORTADATAOUT
q_a[9] <= ram_block2a9.PORTADATAOUT
q_a[10] <= ram_block2a10.PORTADATAOUT
q_a[11] <= ram_block2a11.PORTADATAOUT
q_a[12] <= ram_block2a12.PORTADATAOUT
q_a[13] <= ram_block2a13.PORTADATAOUT
q_a[14] <= ram_block2a14.PORTADATAOUT
q_a[15] <= ram_block2a15.PORTADATAOUT
q_b[0] <= ram_block2a0.PORTBDATAOUT
q_b[1] <= ram_block2a1.PORTBDATAOUT
q_b[2] <= ram_block2a2.PORTBDATAOUT
q_b[3] <= ram_block2a3.PORTBDATAOUT
q_b[4] <= ram_block2a4.PORTBDATAOUT
q_b[5] <= ram_block2a5.PORTBDATAOUT
q_b[6] <= ram_block2a6.PORTBDATAOUT
q_b[7] <= ram_block2a7.PORTBDATAOUT
q_b[8] <= ram_block2a8.PORTBDATAOUT
q_b[9] <= ram_block2a9.PORTBDATAOUT
q_b[10] <= ram_block2a10.PORTBDATAOUT
q_b[11] <= ram_block2a11.PORTBDATAOUT
q_b[12] <= ram_block2a12.PORTBDATAOUT
q_b[13] <= ram_block2a13.PORTBDATAOUT
q_b[14] <= ram_block2a14.PORTBDATAOUT
q_b[15] <= ram_block2a15.PORTBDATAOUT
wren_a => ram_block2a0.PORTAWE
wren_a => ram_block2a1.PORTAWE
wren_a => ram_block2a2.PORTAWE
wren_a => ram_block2a3.PORTAWE
wren_a => ram_block2a4.PORTAWE
wren_a => ram_block2a5.PORTAWE
wren_a => ram_block2a6.PORTAWE
wren_a => ram_block2a7.PORTAWE
wren_a => ram_block2a8.PORTAWE
wren_a => ram_block2a9.PORTAWE
wren_a => ram_block2a10.PORTAWE
wren_a => ram_block2a11.PORTAWE
wren_a => ram_block2a12.PORTAWE
wren_a => ram_block2a13.PORTAWE
wren_a => ram_block2a14.PORTAWE
wren_a => ram_block2a15.PORTAWE
wren_b => ram_block2a0.PORTBRE
wren_b => ram_block2a1.PORTBRE
wren_b => ram_block2a2.PORTBRE
wren_b => ram_block2a3.PORTBRE
wren_b => ram_block2a4.PORTBRE
wren_b => ram_block2a5.PORTBRE
wren_b => ram_block2a6.PORTBRE
wren_b => ram_block2a7.PORTBRE
wren_b => ram_block2a8.PORTBRE
wren_b => ram_block2a9.PORTBRE
wren_b => ram_block2a10.PORTBRE
wren_b => ram_block2a11.PORTBRE
wren_b => ram_block2a12.PORTBRE
wren_b => ram_block2a13.PORTBRE
wren_b => ram_block2a14.PORTBRE
wren_b => ram_block2a15.PORTBRE


|ram|add:inst2
out_clk => a[0].CLK
out_clk => a[1].CLK
out_clk => a[2].CLK
out_clk => a[3].CLK
out_clk => a[4].CLK
out_clk => a[5].CLK
out_clk => a[6].CLK
out_clk => a[7].CLK
addr[0] <= a[0].DB_MAX_OUTPUT_PORT_TYPE
addr[1] <= a[1].DB_MAX_OUTPUT_PORT_TYPE
addr[2] <= a[2].DB_MAX_OUTPUT_PORT_TYPE
addr[3] <= a[3].DB_MAX_OUTPUT_PORT_TYPE
addr[4] <= a[4].DB_MAX_OUTPUT_PORT_TYPE
addr[5] <= a[5].DB_MAX_OUTPUT_PORT_TYPE
addr[6] <= a[6].DB_MAX_OUTPUT_PORT_TYPE
addr[7] <= a[7].DB_MAX_OUTPUT_PORT_TYPE