ram.hier_info

ram的vhdl源代码在colloy实现

|ram
q[0] <= memory:inst.q[0]
q[1] <= memory:inst.q[1]
q[2] <= memory:inst.q[2]
q[3] <= memory:inst.q[3]
q[4] <= memory:inst.q[4]
q[5] <= memory:inst.q[5]
q[6] <= memory:inst.q[6]
q[7] <= memory:inst.q[7]
q[8] <= memory:inst.q[8]
q[9] <= memory:inst.q[9]
q[10] <= memory:inst.q[10]
q[11] <= memory:inst.q[11]
q[12] <= memory:inst.q[12]
q[13] <= memory:inst.q[13]
q[14] <= memory:inst.q[14]
q[15] <= memory:inst.q[15]
wr => memory:inst.wren
wr => inst3.IN0
ce => inst1.IN0
out_clk => memory:inst.rdclock
out_clk => add:inst2.out_clk
data[0] => memory:inst.data[0]
data[1] => memory:inst.data[1]
data[2] => memory:inst.data[2]
data[3] => memory:inst.data[3]
data[4] => memory:inst.data[4]
data[5] => memory:inst.data[5]
data[6] => memory:inst.data[6]
data[7] => memory:inst.data[7]
data[8] => memory:inst.data[8]
data[9] => memory:inst.data[9]
data[10] => memory:inst.data[10]
data[11] => memory:inst.data[11]
data[12] => memory:inst.data[12]
data[13] => memory:inst.data[13]
data[14] => memory:inst.data[14]
data[15] => memory:inst.data[15]
addr[0] => memory:inst.wraddress[0]
addr[1] => memory:inst.wraddress[1]
addr[2] => memory:inst.wraddress[2]
addr[3] => memory:inst.wraddress[3]
addr[4] => memory:inst.wraddress[4]
addr[5] => memory:inst.wraddress[5]
addr[6] => memory:inst.wraddress[6]
addr[7] => memory:inst.wraddress[7]


|ram|memory:inst
data[0] => altsyncram:altsyncram_component.data_a[0]
data[1] => altsyncram:altsyncram_component.data_a[1]
data[2] => altsyncram:altsyncram_component.data_a[2]
data[3] => altsyncram:altsyncram_component.data_a[3]
data[4] => altsyncram:altsyncram_component.data_a[4]
data[5] => altsyncram:altsyncram_component.data_a[5]
data[6] => altsyncram:altsyncram_component.data_a[6]
data[7] => altsyncram:altsyncram_component.data_a[7]
data[8] => altsyncram:altsyncram_component.data_a[8]
data[9] => altsyncram:altsyncram_component.data_a[9]
data[10] => altsyncram:altsyncram_component.data_a[10]
data[11] => altsyncram:altsyncram_component.data_a[11]
data[12] => altsyncram:altsyncram_component.data_a[12]
data[13] => altsyncram:altsyncram_component.data_a[13]
data[14] => altsyncram:altsyncram_component.data_a[14]
data[15] => altsyncram:altsyncram_component.data_a[15]
rdaddress[0] => altsyncram:altsyncram_component.address_b[0]
rdaddress[1] => altsyncram:altsyncram_component.address_b[1]
rdaddress[2] => altsyncram:altsyncram_component.address_b[2]
rdaddress[3] => altsyncram:altsyncram_component.address_b[3]
rdaddress[4] => altsyncram:altsyncram_component.address_b[4]
rdaddress[5] => altsyncram:altsyncram_component.address_b[5]
rdaddress[6] => altsyncram:altsyncram_component.address_b[6]
rdaddress[7] => altsyncram:altsyncram_component.address_b[7]
rdclock => altsyncram:altsyncram_component.clock1
wraddress[0] => altsyncram:altsyncram_component.address_a[0]
wraddress[1] => altsyncram:altsyncram_component.address_a[1]
wraddress[2] => altsyncram:altsyncram_component.address_a[2]
wraddress[3] => altsyncram:altsyncram_component.address_a[3]
wraddress[4] => altsyncram:altsyncram_component.address_a[4]
wraddress[5] => altsyncram:altsyncram_component.address_a[5]
wraddress[6] => altsyncram:altsyncram_component.address_a[6]
wraddress[7] => altsyncram:altsyncram_component.address_a[7]
wrclock => altsyncram:altsyncram_component.clock0
wren => altsyncram:altsyncram_component.wren_a
q[0] <= altsyncram:altsyncram_component.q_b[0]
q[1] <= altsyncram:altsyncram_component.q_b[1]
q[2] <= altsyncram:altsyncram_component.q_b[2]
q[3] <= altsyncram:altsyncram_component.q_b[3]
q[4] <= altsyncram:altsyncram_component.q_b[4]
q[5] <= altsyncram:altsyncram_component.q_b[5]
q[6] <= altsyncram:altsyncram_component.q_b[6]
q[7] <= altsyncram:altsyncram_component.q_b[7]
q[8] <= altsyncram:altsyncram_component.q_b[8]
q[9] <= altsyncram:altsyncram_component.q_b[9]
q[10] <= altsyncram:altsyncram_component.q_b[10]
q[11] <= altsyncram:altsyncram_component.q_b[11]
q[12] <= altsyncram:altsyncram_component.q_b[12]
q[13] <= altsyncram:altsyncram_component.q_b[13]
q[14] <= altsyncram:altsyncram_component.q_b[14]
q[15] <= altsyncram:altsyncram_component.q_b[15]


|ram|memory:inst|altsyncram:altsyncram_component
wren_a => altsyncram_qto1:auto_generated.wren_a
rden_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => altsyncram_qto1:auto_generated.data_a[0]
data_a[1] => altsyncram_qto1:auto_generated.data_a[1]
data_a[2] => altsyncram_qto1:auto_generated.data_a[2]
data_a[3] => altsyncram_qto1:auto_generated.data_a[3]
data_a[4] => altsyncram_qto1:auto_generated.data_a[4]
data_a[5] => altsyncram_qto1:auto_generated.data_a[5]
data_a[6] => altsyncram_qto1:auto_generated.data_a[6]
data_a[7] => altsyncram_qto1:auto_generated.data_a[7]
data_a[8] => altsyncram_qto1:auto_generated.data_a[8]
data_a[9] => altsyncram_qto1:auto_generated.data_a[9]
data_a[10] => altsyncram_qto1:auto_generated.data_a[10]
data_a[11] => altsyncram_qto1:auto_generated.data_a[11]
data_a[12] => altsyncram_qto1:auto_generated.data_a[12]
data_a[13] => altsyncram_qto1:auto_generated.data_a[13]
data_a[14] => altsyncram_qto1:auto_generated.data_a[14]
data_a[15] => altsyncram_qto1:auto_generated.data_a[15]
data_b[0] => ~NO_FANOUT~
data_b[1] => ~NO_FANOUT~
data_b[2] => ~NO_FANOUT~
data_b[3] => ~NO_FANOUT~
data_b[4] => ~NO_FANOUT~
data_b[5] => ~NO_FANOUT~
data_b[6] => ~NO_FANOUT~
data_b[7] => ~NO_FANOUT~
data_b[8] => ~NO_FANOUT~
data_b[9] => ~NO_FANOUT~
data_b[10] => ~NO_FANOUT~
data_b[11] => ~NO_FANOUT~
data_b[12] => ~NO_FANOUT~
data_b[13] => ~NO_FANOUT~
data_b[14] => ~NO_FANOUT~
data_b[15] => ~NO_FANOUT~
address_a[0] => altsyncram_qto1:auto_generated.address_a[0]
address_a[1] => altsyncram_qto1:auto_generated.address_a[1]
address_a[2] => altsyncram_qto1:auto_generated.address_a[2]
address_a[3] => altsyncram_qto1:auto_generated.address_a[3]
address_a[4] => altsyncram_qto1:auto_generated.address_a[4]
address_a[5] => altsyncram_qto1:auto_generated.address_a[5]
address_a[6] => altsyncram_qto1:auto_generated.address_a[6]
address_a[7] => altsyncram_qto1:auto_generated.address_a[7]
address_b[0] => altsyncram_qto1:auto_generated.address_b[0]
address_b[1] => altsyncram_qto1:auto_generated.address_b[1]
address_b[2] => altsyncram_qto1:auto_generated.address_b[2]
address_b[3] => altsyncram_qto1:auto_generated.address_b[3]
address_b[4] => altsyncram_qto1:auto_generated.address_b[4]
address_b[5] => altsyncram_qto1:auto_generated.address_b[5]
address_b[6] => altsyncram_qto1:auto_generated.address_b[6]
address_b[7] => altsyncram_qto1:auto_generated.address_b[7]
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_qto1:auto_generated.clock0
clock1 => altsyncram_qto1:auto_generated.clock1
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= <GND>
q_a[1] <= <GND>
q_a[2] <= <GND>
q_a[3] <= <GND>
q_a[4] <= <GND>
q_a[5] <= <GND>
q_a[6] <= <GND>
q_a[7] <= <GND>
q_a[8] <= <GND>
q_a[9] <= <GND>
q_a[10] <= <GND>
q_a[11] <= <GND>
q_a[12] <= <GND>
q_a[13] <= <GND>
q_a[14] <= <GND>
q_a[15] <= <GND>
q_b[0] <= altsyncram_qto1:auto_generated.q_b[0]
q_b[1] <= altsyncram_qto1:auto_generated.q_b[1]
q_b[2] <= altsyncram_qto1:auto_generated.q_b[2]
q_b[3] <= altsyncram_qto1:auto_generated.q_b[3]
q_b[4] <= altsyncram_qto1:auto_generated.q_b[4]
q_b[5] <= altsyncram_qto1:auto_generated.q_b[5]
q_b[6] <= altsyncram_qto1:auto_generated.q_b[6]
q_b[7] <= altsyncram_qto1:auto_generated.q_b[7]
q_b[8] <= altsyncram_qto1:auto_generated.q_b[8]
q_b[9] <= altsyncram_qto1:auto_generated.q_b[9]
q_b[10] <= altsyncram_qto1:auto_generated.q_b[10]
q_b[11] <= altsyncram_qto1:auto_generated.q_b[11]
q_b[12] <= altsyncram_qto1:auto_generated.q_b[12]
q_b[13] <= altsyncram_qto1:auto_generated.q_b[13]
q_b[14] <= altsyncram_qto1:auto_generated.q_b[14]
q_b[15] <= altsyncram_qto1:auto_generated.q_b[15]
eccstatus[0] <= <GND>
eccstatus[1] <= <GND>
eccstatus[2] <= <GND>


|ram|memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated
address_a[0] => altsyncram_m5s1:altsyncram1.address_b[0]
address_a[1] => altsyncram_m5s1:altsyncram1.address_b[1]
address_a[2] => altsyncram_m5s1:altsyncram1.address_b[2]
address_a[3] => altsyncram_m5s1:altsyncram1.address_b[3]
address_a[4] => altsyncram_m5s1:altsyncram1.address_b[4]
address_a[5] => altsyncram_m5s1:altsyncram1.address_b[5]
address_a[6] => altsyncram_m5s1:altsyncram1.address_b[6]
address_a[7] => altsyncram_m5s1:altsyncram1.address_b[7]
address_b[0] => altsyncram_m5s1:altsyncram1.address_a[0]
address_b[1] => altsyncram_m5s1:altsyncram1.address_a[1]
address_b[2] => altsyncram_m5s1:altsyncram1.address_a[2]
address_b[3] => altsyncram_m5s1:altsyncram1.address_a[3]
address_b[4] => altsyncram_m5s1:altsyncram1.address_a[4]
address_b[5] => altsyncram_m5s1:altsyncram1.address_a[5]
address_b[6] => altsyncram_m5s1:altsyncram1.address_a[6]
address_b[7] => altsyncram_m5s1:altsyncram1.address_a[7]
clock0 => altsyncram_m5s1:altsyncram1.clock1
clock1 => altsyncram_m5s1:altsyncram1.clock0
data_a[0] => altsyncram_m5s1:altsyncram1.data_b[0]
data_a[1] => altsyncram_m5s1:altsyncram1.data_b[1]
data_a[2] => altsyncram_m5s1:altsyncram1.data_b[2]
data_a[3] => altsyncram_m5s1:altsyncram1.data_b[3]
data_a[4] => altsyncram_m5s1:altsyncram1.data_b[4]
data_a[5] => altsyncram_m5s1:altsyncram1.data_b[5]
data_a[6] => altsyncram_m5s1:altsyncram1.data_b[6]
data_a[7] => altsyncram_m5s1:altsyncram1.data_b[7]
data_a[8] => altsyncram_m5s1:altsyncram1.data_b[8]
data_a[9] => altsyncram_m5s1:altsyncram1.data_b[9]
data_a[10] => altsyncram_m5s1:altsyncram1.data_b[10]
data_a[11] => altsyncram_m5s1:altsyncram1.data_b[11]
data_a[12] => altsyncram_m5s1:altsyncram1.data_b[12]
data_a[13] => altsyncram_m5s1:altsyncram1.data_b[13]
data_a[14] => altsyncram_m5s1:altsyncram1.data_b[14]
data_a[15] => altsyncram_m5s1:altsyncram1.data_b[15]
q_b[0] <= altsyncram_m5s1:altsyncram1.q_a[0]
q_b[1] <= altsyncram_m5s1:altsyncram1.q_a[1]
q_b[2] <= altsyncram_m5s1:altsyncram1.q_a[2]
q_b[3] <= altsyncram_m5s1:altsyncram1.q_a[3]
q_b[4] <= altsyncram_m5s1:altsyncram1.q_a[4]
q_b[5] <= altsyncram_m5s1:altsyncram1.q_a[5]
q_b[6] <= altsyncram_m5s1:altsyncram1.q_a[6]
q_b[7] <= altsyncram_m5s1:altsyncram1.q_a[7]
q_b[8] <= altsyncram_m5s1:altsyncram1.q_a[8]
q_b[9] <= altsyncram_m5s1:altsyncram1.q_a[9]
q_b[10] <= altsyncram_m5s1:altsyncram1.q_a[10]
q_b[11] <= altsyncram_m5s1:altsyncram1.q_a[11]
q_b[12] <= altsyncram_m5s1:altsyncram1.q_a[12]
q_b[13] <= altsyncram_m5s1:altsyncram1.q_a[13]
q_b[14] <= altsyncram_m5s1:altsyncram1.q_a[14]
q_b[15] <= altsyncram_m5s1:altsyncram1.q_a[15]
wren_a => altsyncram_m5s1:altsyncram1.clocken1
wren_a => altsyncram_m5s1:altsyncram1.wren_b


|ram|memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1
address_a[0] => ram_block2a0.PORTAADDR
address_a[0] => ram_block2a1.PORTAADDR
address_a[0] => ram_block2a2.PORTAADDR
address_a[0] => ram_block2a3.PORTAADDR
address_a[0] => ram_block2a4.PORTAADDR
address_a[0] => ram_block2a5.PORTAADDR
address_a[0] => ram_block2a6.PORTAADDR
address_a[0] => ram_block2a7.PORTAADDR
address_a[0] => ram_block2a8.PORTAADDR
address_a[0] => ram_block2a9.PORTAADDR
address_a[0] => ram_block2a10.PORTAADDR
address_a[0] => ram_block2a11.PORTAADDR
address_a[0] => ram_block2a12.PORTAADDR
address_a[0] => ram_block2a13.PORTAADDR
address_a[0] => ram_block2a14.PORTAADDR
address_a[0] => ram_block2a15.PORTAADDR
address_a[1] => ram_block2a0.PORTAADDR1
address_a[1] => ram_block2a1.PORTAADDR1
address_a[1] => ram_block2a2.PORTAADDR1
address_a[1] => ram_block2a3.PORTAADDR1
address_a[1] => ram_block2a4.PORTAADDR1
address_a[1] => ram_block2a5.PORTAADDR1
address_a[1] => ram_block2a6.PORTAADDR1
address_a[1] => ram_block2a7.PORTAADDR1
address_a[1] => ram_block2a8.PORTAADDR1
address_a[1] => ram_block2a9.PORTAADDR1
address_a[1] => ram_block2a10.PORTAADDR1
address_a[1] => ram_block2a11.PORTAADDR1
address_a[1] => ram_block2a12.PORTAADDR1
address_a[1] => ram_block2a13.PORTAADDR1
address_a[1] => ram_block2a14.PORTAADDR1
address_a[1] => ram_block2a15.PORTAADDR1
address_a[2] => ram_block2a0.PORTAADDR2
address_a[2] => ram_block2a1.PORTAADDR2
address_a[2] => ram_block2a2.PORTAADDR2
address_a[2] => ram_block2a3.PORTAADDR2
address_a[2] => ram_block2a4.PORTAADDR2
address_a[2] => ram_block2a5.PORTAADDR2
address_a[2] => ram_block2a6.PORTAADDR2
address_a[2] => ram_block2a7.PORTAADDR2
address_a[2] => ram_block2a8.PORTAADDR2
address_a[2] => ram_block2a9.PORTAADDR2
address_a[2] => ram_block2a10.PORTAADDR2
address_a[2] => ram_block2a11.PORTAADDR2
address_a[2] => ram_block2a12.PORTAADDR2
address_a[2] => ram_block2a13.PORTAADDR2
address_a[2] => ram_block2a14.PORTAADDR2
address_a[2] => ram_block2a15.PORTAADDR2
address_a[3] => ram_block2a0.PORTAADDR3
address_a[3] => ram_block2a1.PORTAADDR3
address_a[3] => ram_block2a2.PORTAADDR3
address_a[3] => ram_block2a3.PORTAADDR3
address_a[3] => ram_block2a4.PORTAADDR3
address_a[3] => ram_block2a5.PORTAADDR3
address_a[3] => ram_block2a6.PORTAADDR3
address_a[3] => ram_block2a7.PORTAADDR3
address_a[3] => ram_block2a8.PORTAADDR3
address_a[3] => ram_block2a9.PORTAADDR3
address_a[3] => ram_block2a10.PORTAADDR3
address_a[3] => ram_block2a11.PORTAADDR3
address_a[3] => ram_block2a12.PORTAADDR3
address_a[3] => ram_block2a13.PORTAADDR3
address_a[3] => ram_block2a14.PORTAADDR3
address_a[3] => ram_block2a15.PORTAADDR3
address_a[4] => ram_block2a0.PORTAADDR4
address_a[4] => ram_block2a1.PORTAADDR4
address_a[4] => ram_block2a2.PORTAADDR4
address_a[4] => ram_block2a3.PORTAADDR4
address_a[4] => ram_block2a4.PORTAADDR4
address_a[4] => ram_block2a5.PORTAADDR4
address_a[4] => ram_block2a6.PORTAADDR4
address_a[4] => ram_block2a7.PORTAADDR4
address_a[4] => ram_block2a8.PORTAADDR4
address_a[4] => ram_block2a9.PORTAADDR4
address_a[4] => ram_block2a10.PORTAADDR4
address_a[4] => ram_block2a11.PORTAADDR4
address_a[4] => ram_block2a12.PORTAADDR4
address_a[4] => ram_block2a13.PORTAADDR4
address_a[4] => ram_block2a14.PORTAADDR4
address_a[4] => ram_block2a15.PORTAADDR4
address_a[5] => ram_block2a0.PORTAADDR5