ram.map.qmsg

ram的vhdl源代码在colloy实现

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 21 08:49:52 2009 " "Info: Processing started: Tue Apr 21 08:49:52 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ram -c ram " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ram -c ram" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "add.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file add.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 add-behav " "Info: Found design unit 1: add-behav" {  } { { "add.vhd" "" { Text "D:/Program Files/altera/test/ram/add.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 add " "Info: Found entity 1: add" {  } { { "add.vhd" "" { Text "D:/Program Files/altera/test/ram/add.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ram.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 ram " "Info: Found entity 1: ram" {  } { { "ram.bdf" "" { Schematic "D:/Program Files/altera/test/ram/ram.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "ram " "Info: Elaborating entity \"ram\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "memory.vhd 2 1 " "Warning: Using design file memory.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 memory-SYN " "Info: Found design unit 1: memory-SYN" {  } { { "memory.vhd" "" { Text "D:/Program Files/altera/test/ram/memory.vhd" 56 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 memory " "Info: Found entity 1: memory" {  } { { "memory.vhd" "" { Text "D:/Program Files/altera/test/ram/memory.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "memory memory:inst " "Info: Elaborating entity \"memory\" for hierarchy \"memory:inst\"" {  } { { "ram.bdf" "inst" { Schematic "D:/Program Files/altera/test/ram/ram.bdf" { { 64 392 648 224 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../70/quartus/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../70/quartus/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "d:/program files/altera/70/quartus/libraries/megafunctions/altsyncram.tdf" 434 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram memory:inst\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"memory:inst\|altsyncram:altsyncram_component\"" {  } { { "memory.vhd" "altsyncram_component" { Text "D:/Program Files/altera/test/ram/memory.vhd" 98 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}