ram.tan.qmsg

ram的vhdl源代码在colloy实现

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "ce memory memory memory:inst\|altsyncram:altsyncram_component\|altsyncram_qto1:auto_generated\|altsyncram_m5s1:altsyncram1\|ram_block2a0~portb_datain_reg0 memory:inst\|altsyncram:altsyncram_component\|altsyncram_qto1:auto_generated\|altsyncram_m5s1:altsyncram1\|ram_block2a0~portb_memory_reg0 163.03 MHz Internal " "Info: Clock \"ce\" Internal fmax is restricted to 163.03 MHz between source memory \"memory:inst\|altsyncram:altsyncram_component\|altsyncram_qto1:auto_generated\|altsyncram_m5s1:altsyncram1\|ram_block2a0~portb_datain_reg0\" and destination memory \"memory:inst\|altsyncram:altsyncram_component\|altsyncram_qto1:auto_generated\|altsyncram_m5s1:altsyncram1\|ram_block2a0~portb_memory_reg0\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "3.067 ns 3.067 ns 6.134 ns " "Info: fmax restricted to Clock High delay (3.067 ns) plus Clock Low delay (3.067 ns) : restricted to 6.134 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.913 ns + Longest memory memory " "Info: + Longest memory to memory delay is 2.913 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns memory:inst\|altsyncram:altsyncram_component\|altsyncram_qto1:auto_generated\|altsyncram_m5s1:altsyncram1\|ram_block2a0~portb_datain_reg0 1 MEM M4K_X17_Y9 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X17_Y9; Fanout = 1; MEM Node = 'memory:inst\|altsyncram:altsyncram_component\|altsyncram_qto1:auto_generated\|altsyncram_m5s1:altsyncram1\|ram_block2a0~portb_datain_reg0'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a0~portb_datain_reg0 } "NODE_NAME" } } { "db/altsyncram_m5s1.tdf" "" { Text "D:/Program Files/altera/test/ram/db/altsyncram_m5s1.tdf" 51 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.913 ns) 2.913 ns memory:inst\|altsyncram:altsyncram_component\|altsyncram_qto1:auto_generated\|altsyncram_m5s1:altsyncram1\|ram_block2a0~portb_memory_reg0 2 MEM M4K_X17_Y9 0 " "Info: 2: + IC(0.000 ns) + CELL(2.913 ns) = 2.913 ns; Loc. = M4K_X17_Y9; Fanout = 0; MEM Node = 'memory:inst\|altsyncram:altsyncram_component\|altsyncram_qto1:auto_generated\|altsyncram_m5s1:altsyncram1\|ram_block2a0~portb_memory_reg0'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.913 ns" { memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a0~portb_datain_reg0 memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a0~portb_memory_reg0 } "NODE_NAME" } } { "db/altsyncram_m5s1.tdf" "" { Text "D:/Program Files/altera/test/ram/db/altsyncram_m5s1.tdf" 51 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.913 ns ( 100.00 % ) " "Info: Total cell delay = 2.913 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.913 ns" { memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a0~portb_datain_reg0 memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a0~portb_memory_reg0 } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.913 ns" { memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a0~portb_datain_reg0 memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a0~portb_memory_reg0 } { 0.000ns 0.000ns } { 0.000ns 2.913ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.037 ns - Smallest " "Info: - Smallest clock skew is -0.037 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "ce destination 5.313 ns + Shortest memory " "Info: + Shortest clock path from clock \"ce\" to destination memory is 5.313 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.975 ns) 0.975 ns ce 1 CLK PIN_16 1 " "Info: 1: + IC(0.000 ns) + CELL(0.975 ns) = 0.975 ns; Loc. = PIN_16; Fanout = 1; CLK Node = 'ce'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ce } "NODE_NAME" } } { "ram.bdf" "" { Schematic "D:/Program Files/altera/test/ram/ram.bdf" { { 208 -280 -112 224 "ce" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.879 ns) + CELL(0.202 ns) 2.056 ns inst3 2 COMB LCCOMB_X1_Y20_N28 1 " "Info: 2: + IC(0.879 ns) + CELL(0.202 ns) = 2.056 ns; Loc. = LCCOMB_X1_Y20_N28; Fanout = 1; COMB Node = 'inst3'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.081 ns" { ce inst3 } "NODE_NAME" } } { "ram.bdf" "" { Schematic "D:/Program Files/altera/test/ram/ram.bdf" { { 152 -16 48 200 "inst3" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.444 ns) + CELL(0.000 ns) 3.500 ns inst3~clkctrl 3 COMB CLKCTRL_G2 41 " "Info: 3: + IC(1.444 ns) + CELL(0.000 ns) = 3.500 ns; Loc. = CLKCTRL_G2; Fanout = 41; COMB Node = 'inst3~clkctrl'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.444 ns" { inst3 inst3~clkctrl } "NODE_NAME" } } { "ram.bdf" "" { Schematic "D:/Program Files/altera/test/ram/ram.bdf" { { 152 -16 48 200 "inst3" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.992 ns) + CELL(0.821 ns) 5.313 ns memory:inst\|altsyncram:altsyncram_component\|altsyncram_qto1:auto_generated\|altsyncram_m5s1:altsyncram1\|ram_block2a0~portb_memory_reg0 4 MEM M4K_X17_Y9 0 " "Info: 4: + IC(0.992 ns) + CELL(0.821 ns) = 5.313 ns; Loc. = M4K_X17_Y9; Fanout = 0; MEM Node = 'memory:inst\|altsyncram:altsyncram_component\|altsyncram_qto1:auto_generated\|altsyncram_m5s1:altsyncram1\|ram_block2a0~portb_memory_reg0'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.813 ns" { inst3~clkctrl memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a0~portb_memory_reg0 } "NODE_NAME" } } { "db/altsyncram_m5s1.tdf" "" { Text "D:/Program Files/altera/test/ram/db/altsyncram_m5s1.tdf" 51 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.998 ns ( 37.61 % ) " "Info: Total cell delay = 1.998 ns ( 37.61 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.315 ns ( 62.39 % ) " "Info: Total interconnect delay = 3.315 ns ( 62.39 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.313 ns" { ce inst3 inst3~clkctrl memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a0~portb_memory_reg0 } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "5.313 ns" { ce ce~combout inst3 inst3~clkctrl memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a0~portb_memory_reg0 } { 0.000ns 0.000ns 0.879ns 1.444ns 0.992ns } { 0.000ns 0.975ns 0.202ns 0.000ns 0.821ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "ce source 5.350 ns - Longest memory " "Info: - Longest clock path from clock \"ce\" to source memory is 5.350 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.975 ns) 0.975 ns ce 1 CLK PIN_16 1 " "Info: 1: + IC(0.000 ns) + CELL(0.975 ns) = 0.975 ns; Loc. = PIN_16; Fanout = 1; CLK Node = 'ce'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ce } "NODE_NAME" } } { "ram.bdf" "" { Schematic "D:/Program Files/altera/test/ram/ram.bdf" { { 208 -280 -112 224 "ce" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.879 ns) + CELL(0.202 ns) 2.056 ns inst3 2 COMB LCCOMB_X1_Y20_N28 1 " "Info: 2: + IC(0.879 ns) + CELL(0.202 ns) = 2.056 ns; Loc. = LCCOMB_X1_Y20_N28; Fanout = 1; COMB Node = 'inst3'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.081 ns" { ce inst3 } "NODE_NAME" } } { "ram.bdf" "" { Schematic "D:/Program Files/altera/test/ram/ram.bdf" { { 152 -16 48 200 "inst3" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.444 ns) + CELL(0.000 ns) 3.500 ns inst3~clkctrl 3 COMB CLKCTRL_G2 41 " "Info: 3: + IC(1.444 ns) + CELL(0.000 ns) = 3.500 ns; Loc. = CLKCTRL_G2; Fanout = 41; COMB Node = 'inst3~clkctrl'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.444 ns" { inst3 inst3~clkctrl } "NODE_NAME" } } { "ram.bdf" "" { Schematic "D:/Program Files/altera/test/ram/ram.bdf" { { 152 -16 48 200 "inst3" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.992 ns) + CELL(0.858 ns) 5.350 ns memory:inst\|altsyncram:altsyncram_component\|altsyncram_qto1:auto_generated\|altsyncram_m5s1:altsyncram1\|ram_block2a0~portb_datain_reg0 4 MEM M4K_X17_Y9 1 " "Info: 4: + IC(0.992 ns) + CELL(0.858 ns) = 5.350 ns; Loc. = M4K_X17_Y9; Fanout = 1; MEM Node = 'memory:inst\|altsyncram:altsyncram_component\|altsyncram_qto1:auto_generated\|altsyncram_m5s1:altsyncram1\|ram_block2a0~portb_datain_reg0'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.850 ns" { inst3~clkctrl memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a0~portb_datain_reg0 } "NODE_NAME" } } { "db/altsyncram_m5s1.tdf" "" { Text "D:/Program Files/altera/test/ram/db/altsyncram_m5s1.tdf" 51 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.035 ns ( 38.04 % ) " "Info: Total cell delay = 2.035 ns ( 38.04 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.315 ns ( 61.96 % ) " "Info: Total interconnect delay = 3.315 ns ( 61.96 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.350 ns" { ce inst3 inst3~clkctrl memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a0~portb_datain_reg0 } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "5.350 ns" { ce ce~combout inst3 inst3~clkctrl memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a0~portb_datain_reg0 } { 0.000ns 0.000ns 0.879ns 1.444ns 0.992ns } { 0.000ns 0.975ns 0.202ns 0.000ns 0.858ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.313 ns" { ce inst3 inst3~clkctrl memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a0~portb_memory_reg0 } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "5.313 ns" { ce ce~combout inst3 inst3~clkctrl memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a0~portb_memory_reg0 } { 0.000ns 0.000ns 0.879ns 1.444ns 0.992ns } { 0.000ns 0.975ns 0.202ns 0.000ns 0.821ns } "" } } { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.350 ns" { ce inst3 inst3~clkctrl memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a0~portb_datain_reg0 } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "5.350 ns" { ce ce~combout inst3 inst3~clkctrl memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a0~portb_datain_reg0 } { 0.000ns 0.000ns 0.879ns 1.444ns 0.992ns } { 0.000ns 0.975ns 0.202ns 0.000ns 0.858ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.260 ns + " "Info: + Micro clock to output delay of source is 0.260 ns" {  } { { "db/altsyncram_m5s1.tdf" "" { Text "D:/Program Files/altera/test/ram/db/altsyncram_m5s1.tdf" 51 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.046 ns + " "Info: + Micro setup delay of destination is 0.046 ns" {  } { { "db/altsyncram_m5s1.tdf" "" { Text "D:/Program Files/altera/test/ram/db/altsyncram_m5s1.tdf" 51 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.913 ns" { memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a0~portb_datain_reg0 memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a0~portb_memory_reg0 } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.913 ns" { memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a0~portb_datain_reg0 memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a0~portb_memory_reg0 } { 0.000ns 0.000ns } { 0.000ns 2.913ns } "" } } { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.313 ns" { ce inst3 inst3~clkctrl memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a0~portb_memory_reg0 } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "5.313 ns" { ce ce~combout inst3 inst3~clkctrl memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a0~portb_memory_reg0 } { 0.000ns 0.000ns 0.879ns 1.444ns 0.992ns } { 0.000ns 0.975ns 0.202ns 0.000ns 0.821ns } "" } } { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.350 ns" { ce inst3 inst3~clkctrl memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a0~portb_datain_reg0 } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "5.350 ns" { ce ce~combout inst3 inst3~clkctrl memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a0~portb_datain_reg0 } { 0.000ns 0.000ns 0.879ns 1.444ns 0.992ns } { 0.000ns 0.975ns 0.202ns 0.000ns 0.858ns } "" } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a0~portb_memory_reg0 } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a0~portb_memory_reg0 } {  } {  } "" } } { "db/altsyncram_m5s1.tdf" "" { Text "D:/Program Files/altera/test/ram/db/altsyncram_m5s1.tdf" 51 2 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "wr memory memory memory:inst\|altsyncram:altsyncram_component\|altsyncram_qto1:auto_generated\|altsyncram_m5s1:altsyncram1\|ram_block2a0~portb_datain_reg0 memory:inst\|altsyncram:altsyncram_component\|altsyncram_qto1:auto_generated\|altsyncram_m5s1:altsyncram1\|ram_block2a0~portb_memory_reg0 163.03 MHz Internal " "Info: Clock \"wr\" Internal fmax is restricted to 163.03 MHz between source memory \"memory:inst\|altsyncram:altsyncram_component\|altsyncram_qto1:auto_generated\|altsyncram_m5s1:altsyncram1\|ram_block2a0~portb_datain_reg0\" and destination memory \"memory:inst\|altsyncram:altsyncram_component\|altsyncram_qto1:auto_generated\|altsyncram_m5s1:altsyncram1\|ram_block2a0~portb_memory_reg0\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "3.067 ns 3.067 ns 6.134 ns " "Info: fmax restricted to Clock High delay (3.067 ns) plus Clock Low delay (3.067 ns) : restricted to 6.134 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.913 ns + Longest memory memory " "Info: + Longest memory to memory delay is 2.913 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns memory:inst\|altsyncram:altsyncram_component\|altsyncram_qto1:auto_generated\|altsyncram_m5s1:altsyncram1\|ram_block2a0~portb_datain_reg0 1 MEM M4K_X17_Y9 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X17_Y9; Fanout = 1; MEM Node = 'memory:inst\|altsyncram:altsyncram_component\|altsyncram_qto1:auto_generated\|altsyncram_m5s1:altsyncram1\|ram_block2a0~portb_datain_reg0'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a0~portb_datain_reg0 } "NODE_NAME" } } { "db/altsyncram_m5s1.tdf" "" { Text "D:/Program Files/altera/test/ram/db/altsyncram_m5s1.tdf" 51 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.913 ns) 2.913 ns memory:inst\|altsyncram:altsyncram_component\|altsyncram_qto1:auto_generated\|altsyncram_m5s1:altsyncram1\|ram_block2a0~portb_memory_reg0 2 MEM M4K_X17_Y9 0 " "Info: 2: + IC(0.000 ns) + CELL(2.913 ns) = 2.913 ns; Loc. = M4K_X17_Y9; Fanout = 0; MEM Node = 'memory:inst\|altsyncram:altsyncram_component\|altsyncram_qto1:auto_generated\|altsyncram_m5s1:altsyncram1\|ram_block2a0~portb_memory_reg0'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.913 ns" { memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a0~portb_datain_reg0 memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a0~portb_memory_reg0 } "NODE_NAME" } } { "db/altsyncram_m5s1.tdf" "" { Text "D:/Program Files/altera/test/ram/db/altsyncram_m5s1.tdf" 51 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.913 ns ( 100.00 % ) " "Info: Total cell delay = 2.913 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.913 ns" { memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a0~portb_datain_reg0 memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a0~portb_memory_reg0 } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "2.913 ns" { memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a0~portb_datain_reg0 memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a0~portb_memory_reg0 } { 0.000ns 0.000ns } { 0.000ns 2.913ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.037 ns - Smallest " "Info: - Smallest clock skew is -0.037 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "wr destination 5.592 ns + Shortest memory " "Info: + Shortest clock path from clock \"wr\" to destination memory is 5.592 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.995 ns) 0.995 ns wr 1 CLK PIN_15 2 " "Info: 1: + IC(0.000 ns) + CELL(0.995 ns) = 0.995 ns; Loc. = PIN_15; Fanout = 2; CLK Node = 'wr'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { wr } "NODE_NAME" } } { "ram.bdf" "" { Schematic "D:/Program Files/altera/test/ram/ram.bdf" { { 120 -280 -112 136 "wr" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.970 ns) + CELL(0.370 ns) 2.335 ns inst3 2 COMB LCCOMB_X1_Y20_N28 1 " "Info: 2: + IC(0.970 ns) + CELL(0.370 ns) = 2.335 ns; Loc. = LCCOMB_X1_Y20_N28; Fanout = 1; COMB Node = 'inst3'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.340 ns" { wr inst3 } "NODE_NAME" } } { "ram.bdf" "" { Schematic "D:/Program Files/altera/test/ram/ram.bdf" { { 152 -16 48 200 "inst3" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.444 ns) + CELL(0.000 ns) 3.779 ns inst3~clkctrl 3 COMB CLKCTRL_G2 41 " "Info: 3: + IC(1.444 ns) + CELL(0.000 ns) = 3.779 ns; Loc. = CLKCTRL_G2; Fanout = 41; COMB Node = 'inst3~clkctrl'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.444 ns" { inst3 inst3~clkctrl } "NODE_NAME" } } { "ram.bdf" "" { Schematic "D:/Program Files/altera/test/ram/ram.bdf" { { 152 -16 48 200 "inst3" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.992 ns) + CELL(0.821 ns) 5.592 ns memory:inst\|altsyncram:altsyncram_component\|altsyncram_qto1:auto_generated\|altsyncram_m5s1:altsyncram1\|ram_block2a0~portb_memory_reg0 4 MEM M4K_X17_Y9 0 " "Info: 4: + IC(0.992 ns) + CELL(0.821 ns) = 5.592 ns; Loc. = M4K_X17_Y9; Fanout = 0; MEM Node = 'memory:inst\|altsyncram:altsyncram_component\|altsyncram_qto1:auto_generated\|altsyncram_m5s1:altsyncram1\|ram_block2a0~portb_memory_reg0'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.813 ns" { inst3~clkctrl memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a0~portb_memory_reg0 } "NODE_NAME" } } { "db/altsyncram_m5s1.tdf" "" { Text "D:/Program Files/altera/test/ram/db/altsyncram_m5s1.tdf" 51 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.186 ns ( 39.09 % ) " "Info: Total cell delay = 2.186 ns ( 39.09 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.406 ns ( 60.91 % ) " "Info: Total interconnect delay = 3.406 ns ( 60.91 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.592 ns" { wr inst3 inst3~clkctrl memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a0~portb_memory_reg0 } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "5.592 ns" { wr wr~combout inst3 inst3~clkctrl memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a0~portb_memory_reg0 } { 0.000ns 0.000ns 0.970ns 1.444ns 0.992ns } { 0.000ns 0.995ns 0.370ns 0.000ns 0.821ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "wr source 5.629 ns - Longest memory " "Info: - Longest clock path from clock \"wr\" to source memory is 5.629 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.995 ns) 0.995 ns wr 1 CLK PIN_15 2 " "Info: 1: + IC(0.000 ns) + CELL(0.995 ns) = 0.995 ns; Loc. = PIN_15; Fanout = 2; CLK Node = 'wr'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { wr } "NODE_NAME" } } { "ram.bdf" "" { Schematic "D:/Program Files/altera/test/ram/ram.bdf" { { 120 -280 -112 136 "wr" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.970 ns) + CELL(0.370 ns) 2.335 ns inst3 2 COMB LCCOMB_X1_Y20_N28 1 " "Info: 2: + IC(0.970 ns) + CELL(0.370 ns) = 2.335 ns; Loc. = LCCOMB_X1_Y20_N28; Fanout = 1; COMB Node = 'inst3'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.340 ns" { wr inst3 } "NODE_NAME" } } { "ram.bdf" "" { Schematic "D:/Program Files/altera/test/ram/ram.bdf" { { 152 -16 48 200 "inst3" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.444 ns) + CELL(0.000 ns) 3.779 ns inst3~clkctrl 3 COMB CLKCTRL_G2 41 " "Info: 3: + IC(1.444 ns) + CELL(0.000 ns) = 3.779 ns; Loc. = CLKCTRL_G2; Fanout = 41; COMB Node = 'inst3~clkctrl'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.444 ns" { inst3 inst3~clkctrl } "NODE_NAME" } } { "ram.bdf" "" { Schematic "D:/Program Files/altera/test/ram/ram.bdf" { { 152 -16 48 200 "inst3" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.992 ns) + CELL(0.858 ns) 5.629 ns memory:inst\|altsyncram:altsyncram_component\|altsyncram_qto1:auto_generated\|altsyncram_m5s1:altsyncram1\|ram_block2a0~portb_datain_reg0 4 MEM M4K_X17_Y9 1 " "Info: 4: + IC(0.992 ns) + CELL(0.858 ns) = 5.629 ns; Loc. = M4K_X17_Y9; Fanout = 1; MEM Node = 'memory:inst\|altsyncram:altsyncram_component\|altsyncram_qto1:auto_generated\|altsyncram_m5s1:altsyncram1\|ram_block2a0~portb_datain_reg0'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.850 ns" { inst3~clkctrl memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a0~portb_datain_reg0 } "NODE_NAME" } } { "db/altsyncram_m5s1.tdf" "" { Text "D:/Program Files/altera/test/ram/db/altsyncram_m5s1.tdf" 51 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.223 ns ( 39.49 % ) " "Info: Total cell delay = 2.223 ns ( 39.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.406 ns ( 60.51 % ) " "Info: Total interconnect delay = 3.406 ns ( 60.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.629 ns" { wr inst3 inst3~clkctrl memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a0~portb_datain_reg0 } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "5.629 ns" { wr wr~combout inst3 inst3~clkctrl memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a0~portb_datain_reg0 } { 0.000ns 0.000ns 0.970ns 1.444ns 0.992ns } { 0.000ns 0.995ns 0.370ns 0.000ns 0.858ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.592 ns" { wr inst3 inst3~clkctrl memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a0~portb_memory_reg0 } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "5.592 ns" { wr wr~combout inst3 inst3~clkctrl memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a0~portb_memory_reg0 } { 0.000ns 0.000ns 0.970ns 1.444ns 0.992ns } { 0.000ns 0.995ns 0.370ns 0.000ns 0.821ns } "" } } { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.629 ns" { wr inst3 inst3~clkctrl memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a0~portb_datain_reg0 } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "5.629 ns" { wr wr~combout inst3 inst3~clkctrl memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a0~portb_datain_reg0 } { 0.000ns 0.000ns 0.970ns 1.444ns 0.992ns } { 0.000ns 0.995ns 0.370ns 0.000ns 0.858ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.260 ns + " "Info: + Micro clock to output delay of source is 0.260 ns" {  } { { "db/altsyncram_m5s1.tdf" "" { Text "D:/Program Files/altera/test/ram/db/altsyncram_m5s1.tdf" 51 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.046 ns + " "Info: + Micro setup delay of destination is 0.046 ns" {  } { { "db/altsyncram_m5s1.tdf" "" { Text "D:/Program Files/altera/test/ram/db/altsyncram_m5s1.tdf" 51 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.913 ns" { memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1|ram_block2a0~portb_datain_reg0 memory:inst