ram.tan.qmsg

ram的vhdl源代码在colloy实现

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "inst3 " "Info: Detected gated clock \"inst3\" as buffer" {  } { { "ram.bdf" "" { Schematic "D:/Program Files/altera/test/ram/ram.bdf" { { 152 -16 48 200 "inst3" "" } } } } { "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "inst3" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "out_clk register sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1\|regoutff register sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|segment_write_addr_adv_ena 161.55 MHz 6.19 ns Internal " "Info: Clock \"out_clk\" has Internal fmax of 161.55 MHz between source register \"sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1\|regoutff\" and destination register \"sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|segment_write_addr_adv_ena\" (period= 6.19 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.939 ns + Longest register register " "Info: + Longest register to register delay is 5.939 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1\|regoutff 1 REG LCFF_X30_Y10_N25 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X30_Y10_N25; Fanout = 1; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1\|regoutff'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1|regoutff } "NODE_NAME" } } { "../../70/quartus/libraries/megafunctions/sld_mbpmg.vhd" "" { Text "D:/Program Files/altera/70/quartus/libraries/megafunctions/sld_mbpmg.vhd" 381 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.501 ns) + CELL(0.614 ns) 2.115 ns sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_level_seq_mgr:ela_level_seq_mgr\|trigger_happened~522 2 COMB LCCOMB_X33_Y13_N16 1 " "Info: 2: + IC(1.501 ns) + CELL(0.614 ns) = 2.115 ns; Loc. = LCCOMB_X33_Y13_N16; Fanout = 1; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_level_seq_mgr:ela_level_seq_mgr\|trigger_happened~522'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.115 ns" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1|regoutff sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~522 } "NODE_NAME" } } { "../../70/quartus/libraries/megafunctions/sld_ela_control.vhd" "" { Text "D:/Program Files/altera/70/quartus/libraries/megafunctions/sld_ela_control.vhd" 917 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.391 ns) + CELL(0.614 ns) 3.120 ns sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_level_seq_mgr:ela_level_seq_mgr\|trigger_happened~526 3 COMB LCCOMB_X33_Y13_N24 1 " "Info: 3: + IC(0.391 ns) + CELL(0.614 ns) = 3.120 ns; Loc. = LCCOMB_X33_Y13_N24; Fanout = 1; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_level_seq_mgr:ela_level_seq_mgr\|trigger_happened~526'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.005 ns" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~522 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~526 } "NODE_NAME" } } { "../../70/quartus/libraries/megafunctions/sld_ela_control.vhd" "" { Text "D:/Program Files/altera/70/quartus/libraries/megafunctions/sld_ela_control.vhd" 917 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.371 ns) + CELL(0.370 ns) 3.861 ns sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_level_seq_mgr:ela_level_seq_mgr\|trigger_happened~529 4 COMB LCCOMB_X33_Y13_N12 2 " "Info: 4: + IC(0.371 ns) + CELL(0.370 ns) = 3.861 ns; Loc. = LCCOMB_X33_Y13_N12; Fanout = 2; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_level_seq_mgr:ela_level_seq_mgr\|trigger_happened~529'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.741 ns" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~526 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~529 } "NODE_NAME" } } { "../../70/quartus/libraries/megafunctions/sld_ela_control.vhd" "" { Text "D:/Program Files/altera/70/quartus/libraries/megafunctions/sld_ela_control.vhd" 917 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.399 ns) + CELL(0.646 ns) 4.906 ns sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_level_seq_mgr:ela_level_seq_mgr\|trigger_happened~531 5 COMB LCCOMB_X33_Y13_N8 6 " "Info: 5: + IC(0.399 ns) + CELL(0.646 ns) = 4.906 ns; Loc. = LCCOMB_X33_Y13_N8; Fanout = 6; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_level_seq_mgr:ela_level_seq_mgr\|trigger_happened~531'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.045 ns" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~529 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~531 } "NODE_NAME" } } { "../../70/quartus/libraries/megafunctions/sld_ela_control.vhd" "" { Text "D:/Program Files/altera/70/quartus/libraries/megafunctions/sld_ela_control.vhd" 917 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.719 ns) + CELL(0.206 ns) 5.831 ns sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|segment_write_addr_adv_ena~116 6 COMB LCCOMB_X34_Y13_N24 1 " "Info: 6: + IC(0.719 ns) + CELL(0.206 ns) = 5.831 ns; Loc. = LCCOMB_X34_Y13_N24; Fanout = 1; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|segment_write_addr_adv_ena~116'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.925 ns" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~531 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena~116 } "NODE_NAME" } } { "../../70/quartus/libraries/megafunctions/sld_ela_control.vhd" "" { Text "D:/Program Files/altera/70/quartus/libraries/megafunctions/sld_ela_control.vhd" 1521 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 5.939 ns sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|segment_write_addr_adv_ena 7 REG LCFF_X34_Y13_N25 3 " "Info: 7: + IC(0.000 ns) + CELL(0.108 ns) = 5.939 ns; Loc. = LCFF_X34_Y13_N25; Fanout = 3; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|segment_write_addr_adv_ena'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena~116 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } "NODE_NAME" } } { "../../70/quartus/libraries/megafunctions/sld_ela_control.vhd" "" { Text "D:/Program Files/altera/70/quartus/libraries/megafunctions/sld_ela_control.vhd" 1521 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.558 ns ( 43.07 % ) " "Info: Total cell delay = 2.558 ns ( 43.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.381 ns ( 56.93 % ) " "Info: Total interconnect delay = 3.381 ns ( 56.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.939 ns" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1|regoutff sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~522 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~526 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~529 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~531 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena~116 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "5.939 ns" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1|regoutff sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~522 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~526 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~529 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~531 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena~116 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } { 0.000ns 1.501ns 0.391ns 0.371ns 0.399ns 0.719ns 0.000ns } { 0.000ns 0.614ns 0.614ns 0.370ns 0.646ns 0.206ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.013 ns - Smallest " "Info: - Smallest clock skew is 0.013 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "out_clk destination 3.151 ns + Shortest register " "Info: + Shortest clock path from clock \"out_clk\" to destination register is 3.151 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.150 ns) 1.150 ns out_clk 1 CLK PIN_209 1 " "Info: 1: + IC(0.000 ns) + CELL(1.150 ns) = 1.150 ns; Loc. = PIN_209; Fanout = 1; CLK Node = 'out_clk'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { out_clk } "NODE_NAME" } } { "ram.bdf" "" { Schematic "D:/Program Files/altera/test/ram/ram.bdf" { { 264 -72 96 280 "out_clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.257 ns) + CELL(0.000 ns) 1.407 ns out_clk~clkctrl 2 COMB CLKCTRL_G10 409 " "Info: 2: + IC(0.257 ns) + CELL(0.000 ns) = 1.407 ns; Loc. = CLKCTRL_G10; Fanout = 409; COMB Node = 'out_clk~clkctrl'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.257 ns" { out_clk out_clk~clkctrl } "NODE_NAME" } } { "ram.bdf" "" { Schematic "D:/Program Files/altera/test/ram/ram.bdf" { { 264 -72 96 280 "out_clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.078 ns) + CELL(0.666 ns) 3.151 ns sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|segment_write_addr_adv_ena 3 REG LCFF_X34_Y13_N25 3 " "Info: 3: + IC(1.078 ns) + CELL(0.666 ns) = 3.151 ns; Loc. = LCFF_X34_Y13_N25; Fanout = 3; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|segment_write_addr_adv_ena'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.744 ns" { out_clk~clkctrl sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } "NODE_NAME" } } { "../../70/quartus/libraries/megafunctions/sld_ela_control.vhd" "" { Text "D:/Program Files/altera/70/quartus/libraries/megafunctions/sld_ela_control.vhd" 1521 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.816 ns ( 57.63 % ) " "Info: Total cell delay = 1.816 ns ( 57.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.335 ns ( 42.37 % ) " "Info: Total interconnect delay = 1.335 ns ( 42.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.151 ns" { out_clk out_clk~clkctrl sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "3.151 ns" { out_clk out_clk~combout out_clk~clkctrl sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } { 0.000ns 0.000ns 0.257ns 1.078ns } { 0.000ns 1.150ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "out_clk source 3.138 ns - Longest register " "Info: - Longest clock path from clock \"out_clk\" to source register is 3.138 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.150 ns) 1.150 ns out_clk 1 CLK PIN_209 1 " "Info: 1: + IC(0.000 ns) + CELL(1.150 ns) = 1.150 ns; Loc. = PIN_209; Fanout = 1; CLK Node = 'out_clk'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { out_clk } "NODE_NAME" } } { "ram.bdf" "" { Schematic "D:/Program Files/altera/test/ram/ram.bdf" { { 264 -72 96 280 "out_clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.257 ns) + CELL(0.000 ns) 1.407 ns out_clk~clkctrl 2 COMB CLKCTRL_G10 409 " "Info: 2: + IC(0.257 ns) + CELL(0.000 ns) = 1.407 ns; Loc. = CLKCTRL_G10; Fanout = 409; COMB Node = 'out_clk~clkctrl'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.257 ns" { out_clk out_clk~clkctrl } "NODE_NAME" } } { "ram.bdf" "" { Schematic "D:/Program Files/altera/test/ram/ram.bdf" { { 264 -72 96 280 "out_clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.065 ns) + CELL(0.666 ns) 3.138 ns sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1\|regoutff 3 REG LCFF_X30_Y10_N25 1 " "Info: 3: + IC(1.065 ns) + CELL(0.666 ns) = 3.138 ns; Loc. = LCFF_X30_Y10_N25; Fanout = 1; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|sld_mbpmg:\\trigger_modules_gen:0:trigger_match\|sld_sbpmg:\\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1\|regoutff'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.731 ns" { out_clk~clkctrl sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1|regoutff } "NODE_NAME" } } { "../../70/quartus/libraries/megafunctions/sld_mbpmg.vhd" "" { Text "D:/Program Files/altera/70/quartus/libraries/megafunctions/sld_mbpmg.vhd" 381 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.816 ns ( 57.87 % ) " "Info: Total cell delay = 1.816 ns ( 57.87 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.322 ns ( 42.13 % ) " "Info: Total interconnect delay = 1.322 ns ( 42.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.138 ns" { out_clk out_clk~clkctrl sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1|regoutff } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "3.138 ns" { out_clk out_clk~combout out_clk~clkctrl sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1|regoutff } { 0.000ns 0.000ns 0.257ns 1.065ns } { 0.000ns 1.150ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.151 ns" { out_clk out_clk~clkctrl sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "3.151 ns" { out_clk out_clk~combout out_clk~clkctrl sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } { 0.000ns 0.000ns 0.257ns 1.078ns } { 0.000ns 1.150ns 0.000ns 0.666ns } "" } } { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.138 ns" { out_clk out_clk~clkctrl sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1|regoutff } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "3.138 ns" { out_clk out_clk~combout out_clk~clkctrl sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1|regoutff } { 0.000ns 0.000ns 0.257ns 1.065ns } { 0.000ns 1.150ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "../../70/quartus/libraries/megafunctions/sld_mbpmg.vhd" "" { Text "D:/Program Files/altera/70/quartus/libraries/megafunctions/sld_mbpmg.vhd" 381 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "../../70/quartus/libraries/megafunctions/sld_ela_control.vhd" "" { Text "D:/Program Files/altera/70/quartus/libraries/megafunctions/sld_ela_control.vhd" 1521 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.939 ns" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1|regoutff sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~522 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~526 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~529 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~531 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena~116 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "5.939 ns" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1|regoutff sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~522 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~526 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~529 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened~531 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena~116 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } { 0.000ns 1.501ns 0.391ns 0.371ns 0.399ns 0.719ns 0.000ns } { 0.000ns 0.614ns 0.614ns 0.370ns 0.646ns 0.206ns 0.108ns } "" } } { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.151 ns" { out_clk out_clk~clkctrl sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "3.151 ns" { out_clk out_clk~combout out_clk~clkctrl sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } { 0.000ns 0.000ns 0.257ns 1.078ns } { 0.000ns 1.150ns 0.000ns 0.666ns } "" } } { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.138 ns" { out_clk out_clk~clkctrl sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1|regoutff } "NODE_NAME" } } { "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/70/quartus/bin/Technology_Viewer.qrui" "3.138 ns" { out_clk out_clk~combout out_clk~clkctrl sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1|regoutff } { 0.000ns 0.000ns 0.257ns 1.065ns } { 0.000ns 1.150ns 0.000ns 0.666ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}