altsyncram_0np1.tdf

ram的vhdl源代码在colloy实现

--altsyncram ADDRESS_REG_B="CLOCK1" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="NORMAL" CLOCK_ENABLE_INPUT_B="BYPASS" CLOCK_ENABLE_OUTPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_B="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone II" LOW_POWER_MODE="AUTO" NUMWORDS_A=256 NUMWORDS_B=256 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="CLOCK1" POWER_UP_UNINITIALIZED="TRUE" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" WIDTH_A=16 WIDTH_B=16 WIDTH_BYTEENA_A=1 WIDTHAD_A=8 WIDTHAD_B=8 address_a address_b clock0 clock1 clocken0 data_a q_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
--VERSION_BEGIN 7.0 cbx_altsyncram 2007:01:25:14:36:16:SJ cbx_cycloneii 2006:09:29:19:03:26:SJ cbx_lpm_add_sub 2006:10:10:22:03:24:SJ cbx_lpm_compare 2006:04:25:14:54:12:SJ cbx_lpm_decode 2006:04:25:15:10:18:SJ cbx_lpm_mux 2006:04:25:15:10:08:SJ cbx_mgl 2006:10:27:16:08:48:SJ cbx_stratix 2006:09:18:10:47:42:SJ cbx_stratixii 2006:10:13:14:01:30:SJ cbx_stratixiii 2006:10:19:19:28:28:SJ cbx_util_mgl 2006:11:03:10:32:30:SJ  VERSION_END


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FUNCTION altsyncram_d5s1 (address_a[7..0], address_b[7..0], clock0, clock1, clocken1, data_a[15..0], data_b[15..0], wren_a, wren_b)
RETURNS ( q_a[15..0], q_b[15..0]);

--synthesis_resources = M4K 1 
OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";

SUBDESIGN altsyncram_0np1
( 
	address_a[7..0]	:	input;
	address_b[7..0]	:	input;
	clock0	:	input;
	clock1	:	input;
	clocken0	:	input;
	data_a[15..0]	:	input;
	q_b[15..0]	:	output;
	wren_a	:	input;
) 
VARIABLE 
	altsyncram1 : altsyncram_d5s1;

BEGIN 
	altsyncram1.address_a[] = address_b[];
	altsyncram1.address_b[] = address_a[];
	altsyncram1.clock0 = clock1;
	altsyncram1.clock1 = clock0;
	altsyncram1.clocken1 = clocken0;
	altsyncram1.data_a[] = B"1111111111111111";
	altsyncram1.data_b[] = data_a[];
	altsyncram1.wren_a = B"0";
	altsyncram1.wren_b = wren_a;
	q_b[] = altsyncram1.q_a[];
END;
--VALID FILE