add.vhd

来自「ram的vhdl源代码在colloy实现」· VHDL 代码 · 共 20 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
----------------------------------
entity add is
  port(out_clk:in std_logic;
       addr:out std_logic_vector(7 downto 0));
end add;
----------------------------------
architecture behav of add is
begin 
process(out_clk)
variable a :std_logic_vector(7 downto 0);
begin
  if(out_clk='1' and out_clk'event)then
    a:=a+'1';
  end if;
addr<=a;
end process;
end behav;