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📄 ram.map.rpt

📁 ram的vhdl源代码在colloy实现
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+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: sld_signaltap:auto_signaltap_0                                                                                                         ;
+-----------------------------+------------------------------------------------------------------------------------------------------------------------------------------+----------------+
; Parameter Name              ; Value                                                                                                                                    ; Type           ;
+-----------------------------+------------------------------------------------------------------------------------------------------------------------------------------+----------------+
; lpm_type                    ; sld_signaltap                                                                                                                            ; String         ;
; sld_node_info               ; 671116800                                                                                                                                ; Untyped        ;
; sld_ip_version              ; 5                                                                                                                                        ; Signed Integer ;
; sld_ip_minor_version        ; 0                                                                                                                                        ; Signed Integer ;
; sld_common_ip_version       ; 0                                                                                                                                        ; Signed Integer ;
; sld_data_bits               ; 40                                                                                                                                       ; Untyped        ;
; sld_trigger_bits            ; 40                                                                                                                                       ; Untyped        ;
; sld_data_bit_cntr_bits      ; 6                                                                                                                                        ; Untyped        ;
; sld_node_crc_bits           ; 32                                                                                                                                       ; Signed Integer ;
; sld_node_crc_hiword         ; 30820                                                                                                                                    ; Untyped        ;
; sld_node_crc_loword         ; 26229                                                                                                                                    ; Untyped        ;
; sld_incremental_routing     ; 0                                                                                                                                        ; Signed Integer ;
; sld_sample_depth            ; 128                                                                                                                                      ; Untyped        ;
; sld_mem_address_bits        ; 7                                                                                                                                        ; Untyped        ;
; sld_ram_block_type          ; AUTO                                                                                                                                     ; String         ;
; sld_trigger_level           ; 1                                                                                                                                        ; Untyped        ;
; sld_trigger_in_enabled      ; 0                                                                                                                                        ; Untyped        ;
; sld_advanced_trigger_entity ; basic,1,                                                                                                                                 ; Untyped        ;
; sld_trigger_level_pipeline  ; 1                                                                                                                                        ; Untyped        ;
; sld_enable_advanced_trigger ; 0                                                                                                                                        ; Untyped        ;
; sld_advanced_trigger_1      ; NONE                                                                                                                                     ; String         ;
; sld_advanced_trigger_2      ; NONE                                                                                                                                     ; String         ;
; sld_advanced_trigger_3      ; NONE                                                                                                                                     ; String         ;
; sld_advanced_trigger_4      ; NONE                                                                                                                                     ; String         ;
; sld_advanced_trigger_5      ; NONE                                                                                                                                     ; String         ;
; sld_advanced_trigger_6      ; NONE                                                                                                                                     ; String         ;
; sld_advanced_trigger_7      ; NONE                                                                                                                                     ; String         ;
; sld_advanced_trigger_8      ; NONE                                                                                                                                     ; String         ;
; sld_advanced_trigger_9      ; NONE                                                                                                                                     ; String         ;
; sld_advanced_trigger_10     ; NONE                                                                                                                                     ; String         ;
; sld_inversion_mask_length   ; 136                                                                                                                                      ; Untyped        ;
; sld_inversion_mask          ; 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; Untyped        ;
; sld_power_up_trigger        ; 0                                                                                                                                        ; Untyped        ;
+-----------------------------+------------------------------------------------------------------------------------------------------------------------------------------+----------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: sld_hub:sld_hub_inst         ;
+--------------------------+----------------------------------+-----------------+
; Parameter Name           ; Value                            ; Type            ;
+--------------------------+----------------------------------+-----------------+
; sld_hub_ip_version       ; 1                                ; Untyped         ;
; sld_hub_ip_minor_version ; 3                                ; Untyped         ;
; sld_common_ip_version    ; 0                                ; Untyped         ;
; device_family            ; Cyclone II                       ; Untyped         ;
; n_nodes                  ; 1                                ; Untyped         ;
; n_sel_bits               ; 1                                ; Untyped         ;
; n_node_ir_bits           ; 8                                ; Untyped         ;
; node_info                ; 00101000000000000110111000000000 ; Unsigned Binary ;
; compilation_mode         ; 1                                ; Untyped         ;
+--------------------------+----------------------------------+-----------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SignalTap II Logic Analyzer Settings                                                                                                                                                                                                                        ;
+----------------+------------------+---------------------+------------------+--------------+----------------+-------------------------+-----------------+------------------+--------------------------+----------------------------+-------------------------+
; Instance Index ; Instance Name    ; Trigger Input Width ; Data Input Width ; Sample Depth ; Trigger Levels ; Advanced Trigger Levels ; Trigger In Used ; Trigger Out Used ; Power-Up Trigger Enabled ; Incremental Trigger Inputs ; Incremental Data Inputs ;
+----------------+------------------+---------------------+------------------+--------------+----------------+-------------------------+-----------------+------------------+--------------------------+----------------------------+-------------------------+
; 0              ; auto_signaltap_0 ; 0                   ; 0                ; 128          ; 1              ; 0                       ; no              ; no               ; no                       ; 0                          ; 0                       ;
+----------------+------------------+---------------------+------------------+--------------+----------------+-------------------------+-----------------+------------------+--------------------------+----------------------------+-------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                                                                                          ;
+---------------------------------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Compilation Hierarchy Node                                                                        ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                                                                                                                                                                                          ;
+---------------------------------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; |ram                                                                                              ; 250 (0)           ; 497 (0)      ; 5120        ; 0            ; 0       ; 0         ; 0    ; 0            ; |ram                                                                                                                                                                                                                                                         ;
;    |sld_signaltap:auto_signaltap_0|                                                               ; 250 (9)           ; 497 (164)    ; 5120        ; 0            ; 0       ; 0         ; 0    ; 0            ; |ram|sld_signaltap:auto_signaltap_0                                                                                                                                                                                                                          ;
;       |altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|                                           ; 0 (0)             ; 0 (0)        ; 5120        ; 0            ; 0       ; 0         ; 0    ; 0            ; |ram|sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram                                                                                                                                                                          ;
;          |altsyncram_5ri2:auto_generated|                                                         ; 0 (0)             ; 0 (0)        ; 5120        ; 0            ; 0       ; 0         ; 0    ; 0            ; |ram|sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_5ri2:auto_generated                                                                                                                                           ;
;       |sld_acquisition_buffer:sld_acquisition_buffer_inst|                                        ; 10 (2)            ; 15 (1)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |ram|sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst                                                                                                                                                                       ;
;          |lpm_counter:\write_address_non_zero_gen:write_pointer_counter|                          ; 8 (0)             ; 7 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |ram|sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter                                                                                                         ;
;             |cntr_djk:auto_generated|                                                             ; 8 (8)             ; 7 (7)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |ram|sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_djk:auto_generated                                                                                 ;
;          |lpm_ff:\gen_non_zero_sample_depth:trigger_address_register|                             ; 0 (0)             ; 7 (7)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |ram|sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_ff:\gen_non_zero_sample_depth:trigger_address_register                                                                                                            ;
;       |sld_ela_control:ela_control|                                                               ; 136 (10)          ; 242 (3)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |ram|sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control                                                                                                                                                                                              ;
;          |lpm_shiftreg:trigger_config_deserialize|                                                ; 0 (0)             ; 16 (16)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |ram|sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|lpm_shiftreg:trigger_config_deserialize                                                                                                                                                      ;
;          |sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm| ; 80 (0)            ; 200 (0)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |ram|sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm                                                                                                       ;
;             |lpm_shiftreg:trigger_condition_deserialize|                                          ; 0 (0)             ; 120 (120)    ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |ram|sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize                                                            ;
;             |sld_mbpmg:\trigger_modules_gen:0:trigger_match|                                      ; 80 (0)            ; 80 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |ram|sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match                                                        ;
;                |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1|                            ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |ram|sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1  ;
;                |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:10:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |ram|sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:10:sm1 ;
;                |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:11:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |ram|sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:11:sm1 ;
;                |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:12:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |ram|sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:12:sm1 ;
;                |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:13:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |ram|sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:13:sm1 ;
;                |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:14:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |ram|sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:14:sm1 ;
;                |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |ram|sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1 ;
;                |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:16:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |ram|sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:16:sm1 ;
;                |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:17:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |ram|sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:17:sm1 ;
;                |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:18:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |ram|sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:18:sm1 ;
;                |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:19:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |ram|sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:19:sm1 ;
;                |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:1:sm1|                            ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |ram|sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:1:sm1  ;
;                |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:20:sm1|                           ; 2 (2)             ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |ram|sld_signaltap:a

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