ram.map.rpt

ram的vhdl源代码在colloy实现

+--------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_5ri2:auto_generated ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                     ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                      ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------+


+-----------------------------------------------------------------------------+
; Source assignments for sld_signaltap:auto_signaltap_0|sld_rom_sr:crc_rom_sr ;
+----------------------+-------+------+---------------------------------------+
; Assignment           ; Value ; From ; To                                    ;
+----------------------+-------+------+---------------------------------------+
; AUTO_ROM_RECOGNITION ; OFF   ; -    ; -                                     ;
+----------------------+-------+------+---------------------------------------+


+----------------------------------------------------------+
; Source assignments for sld_hub:sld_hub_inst              ;
+------------------------------+-------+------+------------+
; Assignment                   ; Value ; From ; To         ;
+------------------------------+-------+------+------------+
; IGNORE_LCELL_BUFFERS         ; OFF   ; -    ; -          ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; OFF   ; -    ; -          ;
; NOT_GATE_PUSH_BACK           ; OFF   ; -    ; CLR_SIGNAL ;
; POWER_UP_LEVEL               ; LOW   ; -    ; CLR_SIGNAL ;
+------------------------------+-------+------+------------+


+---------------------------------------------------------------------+
; Source assignments for sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG ;
+----------------------+-------+------+-------------------------------+
; Assignment           ; Value ; From ; To                            ;
+----------------------+-------+------+-------------------------------+
; AUTO_ROM_RECOGNITION ; OFF   ; -    ; -                             ;
+----------------------+-------+------+-------------------------------+


+------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: memory:inst|altsyncram:altsyncram_component ;
+------------------------------------+----------------------+------------------------------+
; Parameter Name                     ; Value                ; Type                         ;
+------------------------------------+----------------------+------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                      ;
; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                   ;
; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                 ;
; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                 ;
; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE               ;
; WIDTH_BYTEENA                      ; 1                    ; Untyped                      ;
; OPERATION_MODE                     ; DUAL_PORT            ; Untyped                      ;
; WIDTH_A                            ; 16                   ; Signed Integer               ;
; WIDTHAD_A                          ; 8                    ; Signed Integer               ;
; NUMWORDS_A                         ; 256                  ; Signed Integer               ;
; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped                      ;
; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                      ;
; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                      ;
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                      ;
; INDATA_ACLR_A                      ; NONE                 ; Untyped                      ;
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                      ;
; WIDTH_B                            ; 16                   ; Signed Integer               ;
; WIDTHAD_B                          ; 8                    ; Signed Integer               ;
; NUMWORDS_B                         ; 256                  ; Signed Integer               ;
; INDATA_REG_B                       ; CLOCK1               ; Untyped                      ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                      ;
; RDCONTROL_REG_B                    ; CLOCK1               ; Untyped                      ;
; ADDRESS_REG_B                      ; CLOCK1               ; Untyped                      ;
; OUTDATA_REG_B                      ; CLOCK1               ; Untyped                      ;
; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                      ;
; INDATA_ACLR_B                      ; NONE                 ; Untyped                      ;
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                      ;
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                      ;
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                      ;
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                      ;
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                      ;
; WIDTH_BYTEENA_A                    ; 1                    ; Signed Integer               ;
; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                      ;
; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                      ;
; BYTE_SIZE                          ; 8                    ; Untyped                      ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE            ; Untyped                      ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped                      ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                      ;
; INIT_FILE                          ; UNUSED               ; Untyped                      ;
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                      ;
; MAXIMUM_DEPTH                      ; 0                    ; Untyped                      ;
; CLOCK_ENABLE_INPUT_A               ; BYPASS               ; Untyped                      ;
; CLOCK_ENABLE_INPUT_B               ; BYPASS               ; Untyped                      ;
; CLOCK_ENABLE_OUTPUT_A              ; BYPASS               ; Untyped                      ;
; CLOCK_ENABLE_OUTPUT_B              ; BYPASS               ; Untyped                      ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                      ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                      ;
; ENABLE_ECC                         ; FALSE                ; Untyped                      ;
; DEVICE_FAMILY                      ; Cyclone II           ; Untyped                      ;
; CBXI_PARAMETER                     ; altsyncram_qto1      ; Untyped                      ;
+------------------------------------+----------------------+------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".