ram.map.rpt

ram的vhdl源代码在colloy实现

Analysis & Synthesis report for ram
Tue Apr 21 08:50:04 2009
Quartus II Version 7.0 Build 33 02/05/2007 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis RAM Summary
  8. General Register Statistics
  9. Multiplexer Restructuring Statistics (Restructuring Performed)
 10. Source assignments for memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated
 11. Source assignments for memory:inst|altsyncram:altsyncram_component|altsyncram_qto1:auto_generated|altsyncram_m5s1:altsyncram1
 12. Source assignments for sld_signaltap:auto_signaltap_0
 13. Source assignments for sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_5ri2:auto_generated
 14. Source assignments for sld_signaltap:auto_signaltap_0|sld_rom_sr:crc_rom_sr
 15. Source assignments for sld_hub:sld_hub_inst
 16. Source assignments for sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG
 17. Parameter Settings for User Entity Instance: memory:inst|altsyncram:altsyncram_component
 18. Parameter Settings for Inferred Entity Instance: sld_signaltap:auto_signaltap_0
 19. Parameter Settings for Inferred Entity Instance: sld_hub:sld_hub_inst
 20. SignalTap II Logic Analyzer Settings
 21. Analysis & Synthesis Resource Utilization by Entity
 22. Analysis & Synthesis Resource Utilization by Entity
 23. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                 ;
+------------------------------------+-----------------------------------------+
; Analysis & Synthesis Status        ; Successful - Tue Apr 21 08:50:04 2009   ;
; Quartus II Version                 ; 7.0 Build 33 02/05/2007 SJ Full Version ;
; Revision Name                      ; ram                                     ;
; Top-level Entity Name              ; ram                                     ;
; Family                             ; Cyclone II                              ;
; Total logic elements               ; 9                                       ;
;     Total combinational functions  ; 9                                       ;
;     Dedicated logic registers      ; 8                                       ;
; Total registers                    ; N/A until Partition Merge               ;
; Total pins                         ; N/A until Partition Merge               ;
; Total virtual pins                 ; N/A until Partition Merge               ;
; Total memory bits                  ; N/A until Partition Merge               ;
; Embedded Multiplier 9-bit elements ; N/A until Partition Merge               ;
; Total PLLs                         ; N/A until Partition Merge               ;
+------------------------------------+-----------------------------------------+


+--------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Option                                                             ; Setting            ; Default Value      ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Device                                                             ; EP2C20Q240C8       ;                    ;
; Top-level entity name                                              ; ram                ; ram                ;
; Family name                                                        ; Cyclone II         ; Stratix            ;
; Restructure Multiplexers                                           ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                ; Off                ; Off                ;
; Preserve fewer node names                                          ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                          ; Off                ; Off                ;
; Verilog Version                                                    ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                       ; VHDL93             ; VHDL93             ;
; State Machine Processing                                           ; Auto               ; Auto               ;
; Safe State Machine                                                 ; Off                ; Off                ;
; Extract Verilog State Machines                                     ; On                 ; On                 ;
; Extract VHDL State Machines                                        ; On                 ; On                 ;
; Ignore Verilog initial constructs                                  ; Off                ; Off                ;
; Add Pass-Through Logic to Inferred RAMs                            ; On                 ; On                 ;
; DSP Block Balancing                                                ; Auto               ; Auto               ;
; NOT Gate Push-Back                                                 ; On                 ; On                 ;
; Power-Up Don't Care                                                ; On                 ; On                 ;
; Remove Redundant Logic Cells                                       ; Off                ; Off                ;
; Remove Duplicate Registers                                         ; On                 ; On                 ;
; Ignore CARRY Buffers                                               ; Off                ; Off                ;
; Ignore CASCADE Buffers                                             ; Off                ; Off                ;