part1.tan.rpt

This codes is one of my univ projects I ve been working on for 3months. I d like to share it and mak

Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off part1 -c part1 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Info: Clock "CLK" Internal fmax is restricted to 200.0 MHz between source memory "myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_we_reg" and destination memory "myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[0]"
    Info: fmax restricted to Clock High delay (2.5 ns) plus Clock Low delay (2.5 ns) : restricted to 5.0 ns. Expand message to see actual delay path.
        Info: + Longest memory to memory delay is 2.894 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X26_Y1; Fanout = 8; MEM Node = 'myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_we_reg'
            Info: 2: + IC(0.000 ns) + CELL(2.894 ns) = 2.894 ns; Loc. = M4K_X26_Y1; Fanout = 1; MEM Node = 'myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[0]'
            Info: Total cell delay = 2.894 ns ( 100.00 % )
        Info: - Smallest clock skew is -0.026 ns
            Info: + Shortest clock path from clock "CLK" to destination memory is 2.735 ns
                Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N1; Fanout = 1; CLK Node = 'CLK'
                Info: 2: + IC(0.113 ns) + CELL(0.000 ns) = 1.112 ns; Loc. = CLKCTRL_G2; Fanout = 30; COMB Node = 'CLK~clkctrl'
                Info: 3: + IC(0.988 ns) + CELL(0.635 ns) = 2.735 ns; Loc. = M4K_X26_Y1; Fanout = 1; MEM Node = 'myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[0]'
                Info: Total cell delay = 1.634 ns ( 59.74 % )
                Info: Total interconnect delay = 1.101 ns ( 40.26 % )
            Info: - Longest clock path from clock "CLK" to source memory is 2.761 ns
                Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N1; Fanout = 1; CLK Node = 'CLK'
                Info: 2: + IC(0.113 ns) + CELL(0.000 ns) = 1.112 ns; Loc. = CLKCTRL_G2; Fanout = 30; COMB Node = 'CLK~clkctrl'
                Info: 3: + IC(0.988 ns) + CELL(0.661 ns) = 2.761 ns; Loc. = M4K_X26_Y1; Fanout = 8; MEM Node = 'myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_we_reg'
                Info: Total cell delay = 1.660 ns ( 60.12 % )
                Info: Total interconnect delay = 1.101 ns ( 39.88 % )
        Info: + Micro clock to output delay of source is 0.209 ns
        Info: + Micro setup delay of destination is 0.035 ns
Info: tsu for memory "myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg0" (data pin = "Data[0]", clock pin = "CLK") is 3.829 ns
    Info: + Longest pin to memory delay is 6.554 ns
        Info: 1: + IC(0.000 ns) + CELL(0.830 ns) = 0.830 ns; Loc. = PIN_Y13; Fanout = 1; PIN Node = 'Data[0]'
        Info: 2: + IC(5.618 ns) + CELL(0.106 ns) = 6.554 ns; Loc. = M4K_X26_Y1; Fanout = 1; MEM Node = 'myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg0'
        Info: Total cell delay = 0.936 ns ( 14.28 % )
        Info: Total interconnect delay = 5.618 ns ( 85.72 % )
    Info: + Micro setup delay of destination is 0.035 ns
    Info: - Shortest clock path from clock "CLK" to destination memory is 2.760 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N1; Fanout = 1; CLK Node = 'CLK'
        Info: 2: + IC(0.113 ns) + CELL(0.000 ns) = 1.112 ns; Loc. = CLKCTRL_G2; Fanout = 30; COMB Node = 'CLK~clkctrl'
        Info: 3: + IC(0.988 ns) + CELL(0.660 ns) = 2.760 ns; Loc. = M4K_X26_Y1; Fanout = 1; MEM Node = 'myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg0'
        Info: Total cell delay = 1.659 ns ( 60.11 % )
        Info: Total interconnect delay = 1.101 ns ( 39.89 % )
Info: tco from clock "CLK" to destination pin "LED[6]" through memory "myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[6]" is 7.624 ns
    Info: + Longest clock path from clock "CLK" to source memory is 2.735 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N1; Fanout = 1; CLK Node = 'CLK'
        Info: 2: + IC(0.113 ns) + CELL(0.000 ns) = 1.112 ns; Loc. = CLKCTRL_G2; Fanout = 30; COMB Node = 'CLK~clkctrl'
        Info: 3: + IC(0.988 ns) + CELL(0.635 ns) = 2.735 ns; Loc. = M4K_X26_Y1; Fanout = 1; MEM Node = 'myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[6]'
        Info: Total cell delay = 1.634 ns ( 59.74 % )
        Info: Total interconnect delay = 1.101 ns ( 40.26 % )
    Info: + Micro clock to output delay of source is 0.209 ns
    Info: + Longest memory to pin delay is 4.680 ns
        Info: 1: + IC(0.000 ns) + CELL(0.088 ns) = 0.088 ns; Loc. = M4K_X26_Y1; Fanout = 1; MEM Node = 'myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[6]'
        Info: 2: + IC(1.794 ns) + CELL(2.798 ns) = 4.680 ns; Loc. = PIN_AD7; Fanout = 0; PIN Node = 'LED[6]'
        Info: Total cell delay = 2.886 ns ( 61.67 % )
        Info: Total interconnect delay = 1.794 ns ( 38.33 % )
Info: th for memory "myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg1" (data pin = "Data[1]", clock pin = "CLK") is -2.826 ns
    Info: + Longest clock path from clock "CLK" to destination memory is 2.760 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N1; Fanout = 1; CLK Node = 'CLK'
        Info: 2: + IC(0.113 ns) + CELL(0.000 ns) = 1.112 ns; Loc. = CLKCTRL_G2; Fanout = 30; COMB Node = 'CLK~clkctrl'
        Info: 3: + IC(0.988 ns) + CELL(0.660 ns) = 2.760 ns; Loc. = M4K_X26_Y1; Fanout = 1; MEM Node = 'myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg1'
        Info: Total cell delay = 1.659 ns ( 60.11 % )
        Info: Total interconnect delay = 1.101 ns ( 39.89 % )
    Info: + Micro hold delay of destination is 0.234 ns
    Info: - Shortest pin to memory delay is 5.820 ns
        Info: 1: + IC(0.000 ns) + CELL(0.820 ns) = 0.820 ns; Loc. = PIN_AB12; Fanout = 1; PIN Node = 'Data[1]'
        Info: 2: + IC(4.894 ns) + CELL(0.106 ns) = 5.820 ns; Loc. = M4K_X26_Y1; Fanout = 1; MEM Node = 'myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg1'
        Info: Total cell delay = 0.926 ns ( 15.91 % )
        Info: Total interconnect delay = 4.894 ns ( 84.09 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Peak virtual memory: 149 megabytes
    Info: Processing ended: Fri May 22 09:24:21 2009
    Info: Elapsed time: 00:00:02
    Info: Total CPU time (on all processors): 00:00:01