part1.tan.rpt

来自「This codes is one of my univ projects I 」· RPT 代码 · 共 293 行 · 第 1/4 页

; Report IO Paths Separately                                          ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                        ; On                 ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis      ; Off                ;      ;    ;             ;
; Removes common clock path pessimism (CCPP) during slack computation ; Off                ;      ;    ;             ;
; Output I/O Timing Endpoint                                          ; Near End           ;      ;    ;             ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CLK             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK'                                                                                                                                                                                                                                                                                                                                                                        ;
+-------+------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From                                                                                                      ; To                                                                                                       ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_we_reg       ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[0]                         ; CLK        ; CLK      ; None                        ; None                      ; 2.894 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg0 ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[0]                         ; CLK        ; CLK      ; None                        ; None                      ; 2.894 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg1 ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[0]                         ; CLK        ; CLK      ; None                        ; None                      ; 2.894 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg2 ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[0]                         ; CLK        ; CLK      ; None                        ; None                      ; 2.894 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg3 ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[0]                         ; CLK        ; CLK      ; None                        ; None                      ; 2.894 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg4 ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[0]                         ; CLK        ; CLK      ; None                        ; None                      ; 2.894 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_we_reg       ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[1]                         ; CLK        ; CLK      ; None                        ; None                      ; 2.894 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg0 ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[1]                         ; CLK        ; CLK      ; None                        ; None                      ; 2.894 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg1 ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[1]                         ; CLK        ; CLK      ; None                        ; None                      ; 2.894 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg2 ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[1]                         ; CLK        ; CLK      ; None                        ; None                      ; 2.894 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg3 ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[1]                         ; CLK        ; CLK      ; None                        ; None                      ; 2.894 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg4 ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[1]                         ; CLK        ; CLK      ; None                        ; None                      ; 2.894 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_we_reg       ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[2]                         ; CLK        ; CLK      ; None                        ; None                      ; 2.894 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg0 ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[2]                         ; CLK        ; CLK      ; None                        ; None                      ; 2.894 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg1 ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[2]                         ; CLK        ; CLK      ; None                        ; None                      ; 2.894 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg2 ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[2]                         ; CLK        ; CLK      ; None                        ; None                      ; 2.894 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg3 ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[2]                         ; CLK        ; CLK      ; None                        ; None                      ; 2.894 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg4 ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[2]                         ; CLK        ; CLK      ; None                        ; None                      ; 2.894 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_we_reg       ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[3]                         ; CLK        ; CLK      ; None                        ; None                      ; 2.894 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg0 ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[3]                         ; CLK        ; CLK      ; None                        ; None                      ; 2.894 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg1 ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[3]                         ; CLK        ; CLK      ; None                        ; None                      ; 2.894 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg2 ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[3]                         ; CLK        ; CLK      ; None                        ; None                      ; 2.894 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg3 ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[3]                         ; CLK        ; CLK      ; None                        ; None                      ; 2.894 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg4 ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[3]                         ; CLK        ; CLK      ; None                        ; None                      ; 2.894 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_we_reg       ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[4]                         ; CLK        ; CLK      ; None                        ; None                      ; 2.894 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg0 ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[4]                         ; CLK        ; CLK      ; None                        ; None                      ; 2.894 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg1 ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[4]                         ; CLK        ; CLK      ; None                        ; None                      ; 2.894 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg2 ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[4]                         ; CLK        ; CLK      ; None                        ; None                      ; 2.894 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg3 ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[4]                         ; CLK        ; CLK      ; None                        ; None                      ; 2.894 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg4 ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[4]                         ; CLK        ; CLK      ; None                        ; None                      ; 2.894 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_we_reg       ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[5]                         ; CLK        ; CLK      ; None                        ; None                      ; 2.894 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg0 ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[5]                         ; CLK        ; CLK      ; None                        ; None                      ; 2.894 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg1 ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[5]                         ; CLK        ; CLK      ; None                        ; None                      ; 2.894 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg2 ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[5]                         ; CLK        ; CLK      ; None                        ; None                      ; 2.894 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg3 ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[5]                         ; CLK        ; CLK      ; None                        ; None                      ; 2.894 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg4 ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[5]                         ; CLK        ; CLK      ; None                        ; None                      ; 2.894 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_we_reg       ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[6]                         ; CLK        ; CLK      ; None                        ; None                      ; 2.894 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg0 ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[6]                         ; CLK        ; CLK      ; None                        ; None                      ; 2.894 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg1 ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[6]                         ; CLK        ; CLK      ; None                        ; None                      ; 2.894 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg2 ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[6]                         ; CLK        ; CLK      ; None                        ; None                      ; 2.894 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg3 ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[6]                         ; CLK        ; CLK      ; None                        ; None                      ; 2.894 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg4 ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[6]                         ; CLK        ; CLK      ; None                        ; None                      ; 2.894 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_we_reg       ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[7]                         ; CLK        ; CLK      ; None                        ; None                      ; 2.894 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg0 ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[7]                         ; CLK        ; CLK      ; None                        ; None                      ; 2.894 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg1 ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[7]                         ; CLK        ; CLK      ; None                        ; None                      ; 2.894 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg2 ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[7]                         ; CLK        ; CLK      ; None                        ; None                      ; 2.894 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg3 ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[7]                         ; CLK        ; CLK      ; None                        ; None                      ; 2.894 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg4 ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[7]                         ; CLK        ; CLK      ; None                        ; None                      ; 2.894 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg0  ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_memory_reg0 ; CLK        ; CLK      ; None                        ; None                      ; 2.645 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg1  ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a1~porta_memory_reg0 ; CLK        ; CLK      ; None                        ; None                      ; 2.645 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg2  ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a2~porta_memory_reg0 ; CLK        ; CLK      ; None                        ; None                      ; 2.645 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg3  ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a3~porta_memory_reg0 ; CLK        ; CLK      ; None                        ; None                      ; 2.645 ns                ;