part1.tan.rpt

This codes is one of my univ projects I ve been working on for 3months. I d like to share it and mak

; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg4  ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a4~porta_memory_reg0 ; CLK        ; CLK      ; None                        ; None                      ; 2.645 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg5  ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a5~porta_memory_reg0 ; CLK        ; CLK      ; None                        ; None                      ; 2.645 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg6  ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a6~porta_memory_reg0 ; CLK        ; CLK      ; None                        ; None                      ; 2.645 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg7  ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a7~porta_memory_reg0 ; CLK        ; CLK      ; None                        ; None                      ; 2.645 ns                ;
+-------+------------------------------------------------+-----------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; tsu                                                                                                                                                                   ;
+-------+--------------+------------+------------+-----------------------------------------------------------------------------------------------------------+----------+
; Slack ; Required tsu ; Actual tsu ; From       ; To                                                                                                        ; To Clock ;
+-------+--------------+------------+------------+-----------------------------------------------------------------------------------------------------------+----------+
; N/A   ; None         ; 3.829 ns   ; Data[0]    ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg0  ; CLK      ;
; N/A   ; None         ; 3.821 ns   ; Address[1] ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg1 ; CLK      ;
; N/A   ; None         ; 3.810 ns   ; Address[2] ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg2 ; CLK      ;
; N/A   ; None         ; 3.792 ns   ; Wren       ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_we_reg       ; CLK      ;
; N/A   ; None         ; 3.618 ns   ; Address[0] ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg0 ; CLK      ;
; N/A   ; None         ; 3.593 ns   ; Data[3]    ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg3  ; CLK      ;
; N/A   ; None         ; 3.391 ns   ; Address[4] ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg4 ; CLK      ;
; N/A   ; None         ; 3.372 ns   ; Data[6]    ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg6  ; CLK      ;
; N/A   ; None         ; 3.370 ns   ; Data[5]    ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg5  ; CLK      ;
; N/A   ; None         ; 3.329 ns   ; Data[2]    ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg2  ; CLK      ;
; N/A   ; None         ; 3.325 ns   ; Data[7]    ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg7  ; CLK      ;
; N/A   ; None         ; 3.159 ns   ; Address[3] ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg3 ; CLK      ;
; N/A   ; None         ; 3.101 ns   ; Data[4]    ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg4  ; CLK      ;
; N/A   ; None         ; 3.095 ns   ; Data[1]    ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg1  ; CLK      ;
+-------+--------------+------------+------------+-----------------------------------------------------------------------------------------------------------+----------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; tco                                                                                                                                        ;
+-------+--------------+------------+----------------------------------------------------------------------------------+--------+------------+
; Slack ; Required tco ; Actual tco ; From                                                                             ; To     ; From Clock ;
+-------+--------------+------------+----------------------------------------------------------------------------------+--------+------------+
; N/A   ; None         ; 7.624 ns   ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[6] ; LED[6] ; CLK        ;
; N/A   ; None         ; 7.519 ns   ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[7] ; LED[7] ; CLK        ;
; N/A   ; None         ; 7.496 ns   ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[3] ; LED[3] ; CLK        ;
; N/A   ; None         ; 7.320 ns   ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[5] ; LED[5] ; CLK        ;
; N/A   ; None         ; 7.317 ns   ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[2] ; LED[2] ; CLK        ;
; N/A   ; None         ; 7.307 ns   ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[4] ; LED[4] ; CLK        ;
; N/A   ; None         ; 6.840 ns   ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[0] ; LED[0] ; CLK        ;
; N/A   ; None         ; 6.836 ns   ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|q_a[1] ; LED[1] ; CLK        ;
+-------+--------------+------------+----------------------------------------------------------------------------------+--------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; th                                                                                                                                                                          ;
+---------------+-------------+-----------+------------+-----------------------------------------------------------------------------------------------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From       ; To                                                                                                        ; To Clock ;
+---------------+-------------+-----------+------------+-----------------------------------------------------------------------------------------------------------+----------+
; N/A           ; None        ; -2.826 ns ; Data[1]    ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg1  ; CLK      ;
; N/A           ; None        ; -2.832 ns ; Data[4]    ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg4  ; CLK      ;
; N/A           ; None        ; -2.890 ns ; Address[3] ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg3 ; CLK      ;
; N/A           ; None        ; -3.056 ns ; Data[7]    ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg7  ; CLK      ;
; N/A           ; None        ; -3.060 ns ; Data[2]    ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg2  ; CLK      ;
; N/A           ; None        ; -3.101 ns ; Data[5]    ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg5  ; CLK      ;
; N/A           ; None        ; -3.103 ns ; Data[6]    ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg6  ; CLK      ;
; N/A           ; None        ; -3.122 ns ; Address[4] ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg4 ; CLK      ;
; N/A           ; None        ; -3.324 ns ; Data[3]    ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg3  ; CLK      ;
; N/A           ; None        ; -3.349 ns ; Address[0] ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg0 ; CLK      ;
; N/A           ; None        ; -3.523 ns ; Wren       ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_we_reg       ; CLK      ;
; N/A           ; None        ; -3.541 ns ; Address[2] ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg2 ; CLK      ;
; N/A           ; None        ; -3.552 ns ; Address[1] ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_address_reg1 ; CLK      ;
; N/A           ; None        ; -3.560 ns ; Data[0]    ; myram1:Ram|altsyncram:altsyncram_component|altsyncram_03a1:auto_generated|ram_block1a0~porta_datain_reg0  ; CLK      ;
+---------------+-------------+-----------+------------+-----------------------------------------------------------------------------------------------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 8.1 Build 163 10/28/2008 SJ Web Edition
    Info: Processing started: Fri May 22 09:24:19 2009