part2.tan.rpt

This codes is one of my univ projects I ve been working on for 3months. I d like to share it and mak

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK'                                                                                                                                                                                                                                                                                                                                                                     ;
+-------+------------------------------------------------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From                                                                                                    ; To                                                                                                      ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a0~porta_datain_reg0 ; myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a0~porta_memory_reg0 ; CLK        ; CLK      ; None                        ; None                      ; 2.645 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a0~porta_datain_reg1 ; myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a1~porta_memory_reg0 ; CLK        ; CLK      ; None                        ; None                      ; 2.645 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a0~porta_datain_reg2 ; myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a2~porta_memory_reg0 ; CLK        ; CLK      ; None                        ; None                      ; 2.645 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a0~porta_datain_reg3 ; myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a3~porta_memory_reg0 ; CLK        ; CLK      ; None                        ; None                      ; 2.645 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a0~porta_datain_reg4 ; myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a4~porta_memory_reg0 ; CLK        ; CLK      ; None                        ; None                      ; 2.645 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a0~porta_datain_reg5 ; myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a5~porta_memory_reg0 ; CLK        ; CLK      ; None                        ; None                      ; 2.645 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a0~porta_datain_reg6 ; myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a6~porta_memory_reg0 ; CLK        ; CLK      ; None                        ; None                      ; 2.645 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a0~porta_datain_reg7 ; myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a7~porta_memory_reg0 ; CLK        ; CLK      ; None                        ; None                      ; 2.645 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; cnt[0]                                                                                                  ; cnt[2]                                                                                                  ; CLK        ; CLK      ; None                        ; None                      ; 0.956 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; cnt[0]                                                                                                  ; cnt[1]                                                                                                  ; CLK        ; CLK      ; None                        ; None                      ; 0.705 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; cnt[1]                                                                                                  ; cnt[2]                                                                                                  ; CLK        ; CLK      ; None                        ; None                      ; 0.635 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; cnt[2]                                                                                                  ; cnt[2]                                                                                                  ; CLK        ; CLK      ; None                        ; None                      ; 0.407 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; cnt[0]                                                                                                  ; cnt[0]                                                                                                  ; CLK        ; CLK      ; None                        ; None                      ; 0.407 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; cnt[1]                                                                                                  ; cnt[1]                                                                                                  ; CLK        ; CLK      ; None                        ; None                      ; 0.407 ns                ;
+-------+------------------------------------------------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'SW_A'                                                                                                                                                                                                                                                                                                                                                                    ;
+-------+------------------------------------------------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From                                                                                                    ; To                                                                                                      ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a0~porta_datain_reg0 ; myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a0~porta_memory_reg0 ; SW_A       ; SW_A     ; None                        ; None                      ; 2.645 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a0~porta_datain_reg1 ; myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a1~porta_memory_reg0 ; SW_A       ; SW_A     ; None                        ; None                      ; 2.645 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a0~porta_datain_reg2 ; myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a2~porta_memory_reg0 ; SW_A       ; SW_A     ; None                        ; None                      ; 2.645 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a0~porta_datain_reg3 ; myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a3~porta_memory_reg0 ; SW_A       ; SW_A     ; None                        ; None                      ; 2.645 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a0~porta_datain_reg4 ; myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a4~porta_memory_reg0 ; SW_A       ; SW_A     ; None                        ; None                      ; 2.645 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a0~porta_datain_reg5 ; myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a5~porta_memory_reg0 ; SW_A       ; SW_A     ; None                        ; None                      ; 2.645 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a0~porta_datain_reg6 ; myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a6~porta_memory_reg0 ; SW_A       ; SW_A     ; None                        ; None                      ; 2.645 ns                ;
; N/A   ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a0~porta_datain_reg7 ; myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a7~porta_memory_reg0 ; SW_A       ; SW_A     ; None                        ; None                      ; 2.645 ns                ;
+-------+------------------------------------------------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; tsu                                                                                                                                                                  ;
+-------+--------------+------------+------------+----------------------------------------------------------------------------------------------------------+----------+
; Slack ; Required tsu ; Actual tsu ; From       ; To                                                                                                       ; To Clock ;
+-------+--------------+------------+------------+----------------------------------------------------------------------------------------------------------+----------+
; N/A   ; None         ; 2.785 ns   ; Data[0]    ; myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a0~porta_datain_reg0  ; CLK      ;
; N/A   ; None         ; 2.632 ns   ; Data[4]    ; myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a0~porta_datain_reg4  ; CLK      ;
; N/A   ; None         ; 2.612 ns   ; Data[3]    ; myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a0~porta_datain_reg3  ; CLK      ;
; N/A   ; None         ; 2.594 ns   ; Address[3] ; myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a0~porta_address_reg3 ; CLK      ;
; N/A   ; None         ; 2.588 ns   ; Data[6]    ; myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a0~porta_datain_reg6  ; CLK      ;
; N/A   ; None         ; 2.574 ns   ; Address[4] ; myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a0~porta_address_reg4 ; CLK      ;
; N/A   ; None         ; 2.564 ns   ; Data[7]    ; myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a0~porta_datain_reg7  ; CLK      ;
; N/A   ; None         ; 2.547 ns   ; Data[5]    ; myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a0~porta_datain_reg5  ; CLK      ;
; N/A   ; None         ; 2.547 ns   ; Data[2]    ; myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a0~porta_datain_reg2  ; CLK      ;
; N/A   ; None         ; 2.538 ns   ; Address[0] ; myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a0~porta_address_reg0 ; CLK      ;
; N/A   ; None         ; 2.481 ns   ; Wren       ; myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a0~porta_we_reg       ; CLK      ;
; N/A   ; None         ; 2.465 ns   ; Data[1]    ; myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a0~porta_datain_reg1  ; CLK      ;
; N/A   ; None         ; 2.084 ns   ; Address[2] ; myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a0~porta_address_reg2 ; CLK      ;
; N/A   ; None         ; 2.070 ns   ; Address[1] ; myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a0~porta_address_reg1 ; CLK      ;
; N/A   ; None         ; 1.687 ns   ; Data[0]    ; myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a0~porta_datain_reg0  ; SW_A     ;
; N/A   ; None         ; 1.534 ns   ; Data[4]    ; myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a0~porta_datain_reg4  ; SW_A     ;
; N/A   ; None         ; 1.514 ns   ; Data[3]    ; myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a0~porta_datain_reg3  ; SW_A     ;
; N/A   ; None         ; 1.496 ns   ; Address[3] ; myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a0~porta_address_reg3 ; SW_A     ;
; N/A   ; None         ; 1.490 ns   ; Data[6]    ; myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a0~porta_datain_reg6  ; SW_A     ;
; N/A   ; None         ; 1.476 ns   ; Address[4] ; myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a0~porta_address_reg4 ; SW_A     ;
; N/A   ; None         ; 1.466 ns   ; Data[7]    ; myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a0~porta_datain_reg7  ; SW_A     ;
; N/A   ; None         ; 1.449 ns   ; Data[5]    ; myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a0~porta_datain_reg5  ; SW_A     ;
; N/A   ; None         ; 1.449 ns   ; Data[2]    ; myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a0~porta_datain_reg2  ; SW_A     ;
; N/A   ; None         ; 1.440 ns   ; Address[0] ; myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a0~porta_address_reg0 ; SW_A     ;
; N/A   ; None         ; 1.383 ns   ; Wren       ; myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a0~porta_we_reg       ; SW_A     ;
; N/A   ; None         ; 1.367 ns   ; Data[1]    ; myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a0~porta_datain_reg1  ; SW_A     ;
; N/A   ; None         ; 0.986 ns   ; Address[2] ; myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a0~porta_address_reg2 ; SW_A     ;
; N/A   ; None         ; 0.972 ns   ; Address[1] ; myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a0~porta_address_reg1 ; SW_A     ;
+-------+--------------+------------+------------+----------------------------------------------------------------------------------------------------------+----------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; tco                                                                                                                                                                     ;
+-------+--------------+------------+----------------------------------------------------------------------------------------------------------+-------------+------------+
; Slack ; Required tco ; Actual tco ; From                                                                                                     ; To          ; From Clock ;
+-------+--------------+------------+----------------------------------------------------------------------------------------------------------+-------------+------------+
; N/A   ; None         ; 15.689 ns  ; myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a0~porta_we_reg       ; SEG_DATA[4] ; SW_A       ;
; N/A   ; None         ; 15.689 ns  ; myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a0~porta_address_reg0 ; SEG_DATA[4] ; SW_A       ;
; N/A   ; None         ; 15.689 ns  ; myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a0~porta_address_reg1 ; SEG_DATA[4] ; SW_A       ;
; N/A   ; None         ; 15.689 ns  ; myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a0~porta_address_reg2 ; SEG_DATA[4] ; SW_A       ;
; N/A   ; None         ; 15.689 ns  ; myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a0~porta_address_reg3 ; SEG_DATA[4] ; SW_A       ;
; N/A   ; None         ; 15.689 ns  ; myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a0~porta_address_reg4 ; SEG_DATA[4] ; SW_A       ;
; N/A   ; None         ; 15.594 ns  ; myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a0~porta_we_reg       ; SEG_DATA[2] ; SW_A       ;
; N/A   ; None         ; 15.594 ns  ; myram:Ram|altsyncram:altsyncram_component|altsyncram_dlc1:auto_generated|ram_block1a0~porta_address_reg0 ; SEG_DATA[2] ; SW_A       ;