rs232.v

来自「The objective of this project is to crea」· Verilog 代码 · 共 56 行

//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    19:01:40 05/01/2007 
// Design Name: 
// Module Name:    RS232 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
`include "async_transmitter.v"
							//Inputs		//Outputs
module RS232(CLK, TX, Data, Mode, Done, Addr, OE);

parameter WIDTH = 30, HEIGHT = 20;
parameter MAX_ADDR 	= WIDTH * HEIGHT;
parameter START_ADDR = 0;

input 				CLK, Mode;
input 	[7:0]		Data;

output 				Done, OE,TX;
output	[16:0]	Addr;

reg					Send = 1;
reg		[16:0]	Addr = MAX_ADDR;

wire					Busy, BxorM;

assign BxorM = Busy ^ Mode;
assign Done  = (Addr == MAX_ADDR);
assign OE    = Mode;

async_transmitter	AT(CLK, Send, Data, TX, Busy);

always @ (BxorM)
begin
	Send <= !(Busy || Mode);
	
	if(!Mode)
		Addr <= Addr + 1;
	else
		Addr <= START_ADDR;

end
endmodule