📄 camera.v
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//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:00:43 05/01/2007
// Design Name:
// Module Name: Camera
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
//Inputs //Outputs
module Camera(PCLK, Y, Href, Vsync, Mode, Data, Addr, WE, Done);
input PCLK, Href, Vsync, Mode;
input [7:0] Y;
output WE, Done;
output [7:0] Data;
output [16:0] Addr;
reg Ready = 1;
reg [16:0] Addr = 0;
wire Enable;
assign WE = !Ready;
assign Enable = Href & Ready & PCLK;
assign Data = Y;
assign Done = !Ready;
parameter START_ADDR = 0;
//Waiting for vsync to start a new picture
always @ (negedge Vsync)
begin
Ready = ~Ready & Mode;
end
//Resets Addr or increments it
always @ (Mode or PCLK)
begin
if(Enable)
Addr <= Addr + 1;
if(!Mode)
Addr <= START_ADDR;
end
endmodule
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