root.v

The objective of this project is to create a driver for a camera module (we used the OV7620). After

//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    14:38:08 05/02/2007 
// Design Name: 
// Module Name:    Root 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
`include "RS232.v"
`include "Camera.v"
`include "HexDisplay.v"

module Root(CLK,TX,Data,Addr,PCLK,Y,Href,Vsync,OE,WE,LED,AN,SEG);


	input 				CLK,PCLK,Href,Vsync;
	input		[7:0]		Y;
	
	inout		[7:0]		Data;
	
	output				TX,OE,WE;
	output	[16:0]	Addr;
	output	[7:0]		LED;
	output	[3:0]		AN;
	output	[6:0]		SEG;
	
	reg					Mode = 1;
	reg		[15:0]	VCount = 0;
	
	wire 					SerialOE,CamWE, CamDone, SerialDone,EitherDone;
	wire		[7:0]		Ybus;
	wire 		[16:0]	CamAddrBus,SerialAddrBus;
		
	assign EitherDone = CamDone ^ SerialDone;	
	assign WE			= Mode ? CamWE : 1; 
	assign OE			= Mode ? 1	: SerialOE;
	assign Data 	   = Mode ? Ybus : 8'bz; 
	assign Addr			= Mode ? CamAddrBus : SerialAddrBus;
	assign LED[7:1]	= Addr[6:0];
	assign LED[0]		= Mode;

	RS232 serial(CLK, TX, Data, Mode, SerialDone, SerialAddrBus, SerialOE);
	Camera  cam(PCLK, Y, Href, Vsync, Mode, Ybus, CamAddrBus, CamWE, CamDone);
	HexDisplay hex(CamAddrBus[15:0],CLK,AN,SEG);

	/*always @ (posedge EitherDone)
	begin
		Mode <= ~Mode;
	end*/
	
	always @ (posedge Mode)
		VCount <= VCount + 1;

endmodule