master_decoder.v

来自「amba ahb master decoder」· Verilog 代码 · 共 27 行

module master_decoder(HBUSREQ,HLOCK,HTRANS,HADDR,HWRITE,HSIZE,HBURST,HWDATA,HSEL0,HSEL1,HSEL2,HSEL3,HRESETn,HCLK,HGRANT,HREADY,HRESP,HRDATA,BUSREQ,ADDREQ,WRITE,ADDR,SIZE,BURST,SEL,TRANS,WDATA);

output HBUSREQ,HLOCK,HWRITE,HSEL0,HSEL1,HSEL2,HSEL3;
output [1:0]HTRANS;
output [31:0]HADDR,HWDATA;
output [2:0]HSIZE,HBURST;

input HGRANT,HREADY,HCLK,HRESETn,BUSREQ,ADDREQ,WRITE;
input [31:0]ADDR,WDATA;
input [2:0]SIZE,BURST;
input [1:0]HRESP,SEL,TRANS;
input [31:0]HRDATA;



wire HGRANT,HREADY,HCLK,HRESETn,WRITE;
wire [31:0]ADDR,WDATA;
wire [2:0]SIZE,BURST;
wire [1:0]HRESP,SEL,TRANS;
wire [31:0]HRDATA;

wire [1:0]HSEL;

ahb_master master(HBUSREQ,HLOCK,HTRANS,HADDR,HWRITE,HSIZE,HBURST,HWDATA,HSEL,HRESETn,HCLK,HGRANT,HREADY,HRESP,HRDATA,BUSREQ,ADDREQ,WRITE,ADDR,SIZE,BURST,SEL,TRANS,WDATA);
decoder decoder(HSEL0,HSEL1,HSEL2,HSEL3,HSEL);

endmodule