maxof2.vhd

完整的TPC编译码VHDL程序

LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

ENTITY maxof2 IS
	PORT
	(
		clk		                              : in  std_logic;
  coma                               : in  std_logic_vector(9 downto 0);
  comb                               : in  std_logic_vector(9 downto 0);
  anum,bnum                          : in  std_logic_vector(3 downto 0);
  va,vb                              : in  std_logic;
  lw                                 : out std_logic_vector(9 downto 0);
  lnum                               : out std_logic_vector(3 downto 0);
  valid                              : out std_logic
	);
END entity;

ARCHITECTURE rtl OF maxof2 IS
signal g_flag                : std_logic;
signal vab                   : std_logic_vector(1 downto 0);            
component com 
	PORT
	(
		dataa		: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
		datab		: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
		AgeB		: OUT STD_LOGIC 
	);
END component;
begin
 --process(clk)
 --begin
 --  if clk'event and clk='1' then
      --vatemp<=va;
      --vbtemp<=vb;
	 vab<=va & vb;

 --     coma_temp<=coma;
 --     comb_temp<=comb;
 --     anumtemp<=anum;
 --     bnumtemp<=bnum;
 --  end if;
 --end process;
 com_inst : com PORT MAP (coma,comb,g_flag);
  process(clk)
   begin
    if clk'event and clk='1' then
     case vab is
         when "11"=>valid<='1';
                    case g_flag is
                       when '1'=>lw<=coma;
                                 lnum<=anum;
                       when '0'=>lw<=comb;
                                 lnum<=bnum;
                     end case;
         when "10"=>valid<='1';
                     lw<=coma;
                     lnum<=anum;
         when "01"=>valid<='1';
                     lw<=comb;
                     lnum<=bnum;
         when "00"=>valid<='0';
                    lw<="0000000000";
                    lnum<="0000";
     end case;
    end if;
   end process;

end rtl;