g_div.vhd

完整的TPC编译码VHDL程序

LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

ENTITY g_div IS
PORT
( clk		                              : in  std_logic;
  row_firb                           : in  std_logic;
  row_end                            : in  std_logic;
  seq                                : in  std_logic_vector(3 downto 0);
  synd                               : out std_logic_vector(4 downto 0);
  parity                             : out  std_logic
	);
END entity;
ARCHITECTURE rtl OF g_div IS
signal   reg                  : std_logic_vector(4 downto 0);
signal   first_temp0          : std_logic;
signal   seq_temp0            : std_logic_vector(3 downto 0);
signal   row_end_temp0        : std_logic;
signal   romad                : std_logic_vector(9 downto 0);
signal   parity_temp          : std_logic;
component divtable IS
PORT(
		address		: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
		clock		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
	);
END component;

begin

process(clk)
begin
   if clk'event and clk='1' then
       first_temp0<=row_firb;
       row_end_temp0<=row_end;
       seq_temp0<=seq;
       --tseq<=seq_temp1;

   end if;
end process;

process(first_temp0,reg,seq_temp0)
begin
   romad(9 downto 5)<=row_end_temp0 & seq_temp0;
   case first_temp0 is
      when '1'=>romad(4 downto 0)<="00000";
      when '0'=>romad(4 downto 0)<=reg;
   end case;
end process;
divtable_inst0: divtable port map(romad,clk,reg);


process(clk)
begin
 if clk'event and clk='1' then
  case row_end_temp0 is
    when '0'=>case first_temp0 is
               when '1'=>parity_temp<=seq_temp0(0) xor seq_temp0(1) xor seq_temp0(2)xor seq_temp0(3);
               when '0'=>parity_temp<=parity_temp xor seq_temp0(0) xor seq_temp0(1) xor seq_temp0(2)xor seq_temp0(3);
              end case;
    when '1'=>parity_temp<=parity_temp xor seq_temp0(0) xor seq_temp0(1) xor seq_temp0(2); 
  end case;
 end if;
end process;


process(clk)
begin
   if clk'event and clk='1' then
      case first_temp0 is
          when '1'=>synd <=reg;
          when '0'=>null;
      end case;
      --sreg<=reg;
      case first_temp0 is
          when '1'=>if reg="00000" then
                       parity<=parity_temp;
                    else
                       parity<=not parity_temp;
                    end if;
          when '0'=>null;
      end case;
   end if;
end process;

end rtl;