find_small.vhd

完整的TPC编译码VHDL程序

LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

ENTITY find_small IS
	PORT
	(
	clk		                           : in   std_logic;
	a0,a1,a2,a3                        : in   std_logic_vector(3 downto 0);
    set                                : in   std_logic;
	min0,min1,min2,min3                : out  std_logic_vector(3 downto 0);
    min0num,min1num,min2num,min3num    : out  std_logic_vector(1 downto 0)

	);
END entity;

ARCHITECTURE rtl OF find_small IS
signal d0,d1,d2,d3: std_logic_vector(3 downto 0);
signal com00_min,com01_min,com00_max,com01_max    : std_logic_vector(3 downto 0);
signal com10_min,com11_min,com10_max,com11_max    : std_logic_vector(3 downto 0);
signal com00_minnum,com01_minnum,com00_maxnum,com01_maxnum    : std_logic_vector(1 downto 0);
signal com10_minnum,com11_minnum,com10_maxnum,com11_maxnum    : std_logic_vector(1 downto 0);


begin
process(clk)
begin
  if clk'event and clk='1' then
     d0<=a0;
     d1<=a1;
     d2<=a2;
   case set is
     when '0'=>d3<=a3;
     when '1'=>d3<="1111";
   end case;
  end if;
end process;


process(clk)
begin
  if clk'event and clk='1' then
     if d0<=d1 then --=
        com00_min<=d0;
        com00_minnum<="00";
        com00_max<=d1;
        com00_maxnum<="01";        
      else
        com00_min<=d1;
        com00_minnum<="01";
        com00_max<=d0;
        com00_maxnum<="00";        
      end if;
     if d2<=d3 then --=
        com01_min<=d2;
        com01_minnum<="10";
        com01_max<=d3;
        com01_maxnum<="11";        
      else
        com01_min<=d3;
        com01_minnum<="11";
        com01_max<=d2;
        com01_maxnum<="10";        
      end if;

  end if;
end process;

process(clk)
begin
  if clk'event and clk='1' then
     if com00_min<=com01_min then --=
        com10_min<=com00_min;
        com10_minnum<=com00_minnum;
        com10_max<=com01_min;
        com10_maxnum<=com01_minnum;        
      else
        com10_min<=com01_min;
        com10_minnum<=com01_minnum;
        com10_max<=com00_min;
        com10_maxnum<=com00_minnum;        
      end if;
     if com00_max<=com01_max then --=
        com11_min<=com00_max;
        com11_minnum<=com00_maxnum;
        com11_max<=com01_max;
        com11_maxnum<=com01_maxnum;        
      else
        com11_min<=com01_max;
        com11_minnum<=com01_maxnum;
        com11_max<=com00_max;
        com11_maxnum<=com00_maxnum;        
      end if;


  end if;
end process;

process(clk)
begin
  if clk'event and clk='1' then
        min0<=com10_min;
        min0num<=com10_minnum;
        min3<=com11_max;
        min3num<=com11_maxnum;
     if com10_max<com11_min then 
        min1<=com10_max;
        min1num<=com10_maxnum;
        min2<=com11_min;
        min2num<=com11_minnum; 
      elsif com10_max=com11_min  and com10_maxnum<com11_minnum then
        min1<=com10_max;
        min1num<=com10_maxnum;
        min2<=com11_min;
        min2num<=com11_minnum; 
      else
        min1<=com11_min;
        min1num<=com11_minnum;
        min2<=com10_max;
        min2num<=com10_maxnum;        
     end if;
  end if;
end process;

end rtl;