decoder.vhd

完整的TPC编译码VHDL程序

-- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- PROGRAM "Quartus II"
-- VERSION "Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version"

LIBRARY ieee;
USE ieee.std_logic_1164.all; 

LIBRARY work;

ENTITY decoder IS 
	port
	(
		hclk :  IN  STD_LOGIC;
		symbolclk :  IN  STD_LOGIC;
		sym_enable :  IN  STD_LOGIC;
		Isymbol :  IN  STD_LOGIC_VECTOR(4 downto 0);
		Qsymbol :  IN  STD_LOGIC_VECTOR(4 downto 0);
		outq :  OUT  STD_LOGIC;
		oena :  OUT  STD_LOGIC;
		outclk :  OUT  STD_LOGIC;
		demdata :  OUT  STD_LOGIC
	);
END decoder;

ARCHITECTURE bdf_type OF decoder IS 

component core32
	PORT(clk : IN STD_LOGIC;
		 reset : IN STD_LOGIC;
		 itenum : IN STD_LOGIC_VECTOR(3 downto 0);
		 mid_data : IN STD_LOGIC_VECTOR(19 downto 0);
		 pri_data : IN STD_LOGIC_VECTOR(19 downto 0);
		 tdu0 : OUT STD_LOGIC;
		 tdu1 : OUT STD_LOGIC;
		 tdu2 : OUT STD_LOGIC;
		 tdu3 : OUT STD_LOGIC;
		 twe : OUT STD_LOGIC;
		 t_colad : OUT STD_LOGIC_VECTOR(2 downto 0);
		 t_rowad : OUT STD_LOGIC_VECTOR(5 downto 0);
		 tde0 : OUT STD_LOGIC_VECTOR(9 downto 0);
		 tde1 : OUT STD_LOGIC_VECTOR(9 downto 0);
		 tde2 : OUT STD_LOGIC_VECTOR(9 downto 0);
		 tde3 : OUT STD_LOGIC_VECTOR(9 downto 0);
		 tpri : OUT STD_LOGIC_VECTOR(19 downto 0)
	);
end component;

component dec32
	PORT(clk : IN STD_LOGIC;
		 hclk : IN STD_LOGIC;
		 framestart : IN STD_LOGIC;
		 ite_we : IN STD_LOGIC;
		 Idata : IN STD_LOGIC_VECTOR(4 downto 0);
		 ite_col_adr : IN STD_LOGIC_VECTOR(2 downto 0);
		 ite_row_adr : IN STD_LOGIC_VECTOR(5 downto 0);
		 lle0 : IN STD_LOGIC_VECTOR(9 downto 0);
		 lle1 : IN STD_LOGIC_VECTOR(9 downto 0);
		 lle2 : IN STD_LOGIC_VECTOR(9 downto 0);
		 lle3 : IN STD_LOGIC_VECTOR(9 downto 0);
		 prid : IN STD_LOGIC_VECTOR(19 downto 0);
		 Qdata : IN STD_LOGIC_VECTOR(4 downto 0);
		 fenaout : OUT STD_LOGIC;
		 tite_begin : OUT STD_LOGIC;
		 t_ite_b : OUT STD_LOGIC;
		 tbufre : OUT STD_LOGIC;
		 twe : OUT STD_LOGIC;
		 tre : OUT STD_LOGIC;
		 tromflag0 : OUT STD_LOGIC;
		 tromflag1 : OUT STD_LOGIC;
		 outflag : OUT STD_LOGIC;
		 saveflag : OUT STD_LOGIC;
		 oena : OUT STD_LOGIC;
		 tloopq : OUT STD_LOGIC;
		 ited : OUT STD_LOGIC_VECTOR(19 downto 0);
		 outpri : OUT STD_LOGIC_VECTOR(19 downto 0);
		 tbd0 : OUT STD_LOGIC_VECTOR(4 downto 0);
		 tbd1 : OUT STD_LOGIC_VECTOR(4 downto 0);
		 tbd2 : OUT STD_LOGIC_VECTOR(4 downto 0);
		 tbd3 : OUT STD_LOGIC_VECTOR(4 downto 0);
		 tbrad : OUT STD_LOGIC_VECTOR(8 downto 0);
		 tbuf_q : OUT STD_LOGIC_VECTOR(19 downto 0);
		 tbufq : OUT STD_LOGIC_VECTOR(19 downto 0);
		 tcnt0 : OUT STD_LOGIC_VECTOR(3 downto 0);
		 tcnt1 : OUT STD_LOGIC_VECTOR(4 downto 0);
		 tcnt2 : OUT STD_LOGIC_VECTOR(2 downto 0);
		 tcnt3 : OUT STD_LOGIC_VECTOR(4 downto 0);
		 tcntd3 : OUT STD_LOGIC_VECTOR(5 downto 0);
		 tcount : OUT STD_LOGIC_VECTOR(7 downto 0);
		 tI : OUT STD_LOGIC_VECTOR(4 downto 0);
		 tite_num : OUT STD_LOGIC_VECTOR(3 downto 0);
		 tQ : OUT STD_LOGIC_VECTOR(4 downto 0)
	);
end component;

component outbuf
	PORT(inclk : IN STD_LOGIC;
		 outclk : IN STD_LOGIC;
		 turn : IN STD_LOGIC;
		 we : IN STD_LOGIC;
		 lu0 : IN STD_LOGIC;
		 lu1 : IN STD_LOGIC;
		 lu2 : IN STD_LOGIC;
		 lu3 : IN STD_LOGIC;
		 save_ena : IN STD_LOGIC;
		 iteration_num : IN STD_LOGIC_VECTOR(3 downto 0);
		 wcol : IN STD_LOGIC_VECTOR(2 downto 0);
		 wrow : IN STD_LOGIC_VECTOR(5 downto 0);
		 tre : OUT STD_LOGIC;
		 tre2 : OUT STD_LOGIC;
		 owe0 : OUT STD_LOGIC;
		 owe1 : OUT STD_LOGIC;
		 tramq0 : OUT STD_LOGIC;
		 tramq1 : OUT STD_LOGIC;
		 toutq : OUT STD_LOGIC;
		 out_col : OUT STD_LOGIC_VECTOR(2 downto 0);
		 out_row : OUT STD_LOGIC_VECTOR(5 downto 0);
		 tcnt0 : OUT STD_LOGIC_VECTOR(4 downto 0);
		 tcnt1 : OUT STD_LOGIC_VECTOR(4 downto 0)
	);
end component;

signal	cle0 :  STD_LOGIC_VECTOR(9 downto 0);
signal	cle1 :  STD_LOGIC_VECTOR(9 downto 0);
signal	cle2 :  STD_LOGIC_VECTOR(9 downto 0);
signal	cle3 :  STD_LOGIC_VECTOR(9 downto 0);
signal	cmcol :  STD_LOGIC_VECTOR(2 downto 0);
signal	cmrow :  STD_LOGIC_VECTOR(5 downto 0);
signal	cmwe :  STD_LOGIC;
signal	cpri :  STD_LOGIC_VECTOR(19 downto 0);
signal	dec_itebdly :  STD_LOGIC;
signal	dec_ited :  STD_LOGIC_VECTOR(19 downto 0);
signal	dec_itenum :  STD_LOGIC_VECTOR(3 downto 0);
signal	dec_itep :  STD_LOGIC_VECTOR(19 downto 0);
signal	lu0 :  STD_LOGIC;
signal	lu1 :  STD_LOGIC;
signal	lu2 :  STD_LOGIC;
signal	lu3 :  STD_LOGIC;
signal	outstr :  STD_LOGIC;
signal	savestr :  STD_LOGIC;


BEGIN 
outclk <= symbolclk;



b2v_inst : core32
PORT MAP(clk => hclk,
		 reset => dec_itebdly,
		 itenum => dec_itenum,
		 mid_data => dec_ited,
		 pri_data => dec_itep,
		 tdu0 => lu0,
		 tdu1 => lu1,
		 tdu2 => lu2,
		 tdu3 => lu3,
		 twe => cmwe,
		 t_colad => cmcol,
		 t_rowad => cmrow,
		 tde0 => cle0,
		 tde1 => cle1,
		 tde2 => cle2,
		 tde3 => cle3,
		 tpri => cpri);

b2v_inst1 : dec32
PORT MAP(clk => symbolclk,
		 hclk => hclk,
		 framestart => sym_enable,
		 ite_we => cmwe,
		 Idata => Isymbol,
		 ite_col_adr => cmcol,
		 ite_row_adr => cmrow,
		 lle0 => cle0,
		 lle1 => cle1,
		 lle2 => cle2,
		 lle3 => cle3,
		 prid => cpri,
		 Qdata => Qsymbol,
		 t_ite_b => dec_itebdly,
		 outflag => outstr,
		 saveflag => savestr,
		 oena => oena,
		 tloopq => demdata,
		 ited => dec_ited,
		 outpri => dec_itep,
		 tite_num => dec_itenum);

b2v_inst3 : outbuf
PORT MAP(inclk => hclk,
		 outclk => symbolclk,
		 turn => outstr,
		 we => cmwe,
		 lu0 => lu0,
		 lu1 => lu1,
		 lu2 => lu2,
		 lu3 => lu3,
		 save_ena => savestr,
		 iteration_num => dec_itenum,
		 wcol => cmcol,
		 wrow => cmrow,
		 toutq => outq);

END;