shift_iteb.vhd

来自「完整的TPC编译码VHDL程序」· VHDL 代码 · 共 33 行

LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

ENTITY shift_iteb IS
	PORT
	(
		clk		      : in   std_logic;
	 din        : in   std_logic;
  dout       : out  std_logic
	);
END entity;
ARCHITECTURE rtl OF shift_iteb IS
signal shf0,shf1,shf2,shf3,shf4,shf5,shf6,shf7,shf8,shf9            : std_logic;

begin
 process(clk)
 begin
   if clk'event and clk='1' then
    shf0<=din;
    shf1<=shf0;
    shf2<=shf1;
    shf3<=shf2;
    shf4<=shf3;
    shf5<=shf4;
    shf6<=shf5;
    shf7<=shf6;
    dout<=shf7;
   end if;
 end process;

end rtl;