📄 dec32.vhd
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LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
ENTITY dec32 IS
PORT
(clk : in std_logic;
hclk : in std_logic;
framestart : in std_logic;
Idata,Qdata : in std_logic_vector(4 downto 0);
lle0,lle1,lle2,lle3 : in std_logic_vector(9 downto 0);
ite_col_adr : in std_logic_vector(2 downto 0);
ite_row_adr : in std_logic_vector(5 downto 0);
ite_we : in std_logic;
prid : in std_logic_vector(19 downto 0);
tI,tQ : out std_logic_vector(4 downto 0);
fenaout : out std_logic;
tcount : out std_logic_vector(7 downto 0);
tite_begin : out std_logic;
t_ite_b : out std_logic;
tite_num : out std_logic_vector(3 downto 0);
tcnt0 : out std_logic_vector(3 downto 0);
tcnt1 : out std_logic_vector(4 downto 0);
tcnt2 : out std_logic_vector(2 downto 0);
tcnt3 : out std_logic_vector(4 downto 0);
tcntd3 : out std_logic_vector(5 downto 0);
tbrad : out std_logic_vector(8 downto 0);
tbufre : out std_logic;
twe,tre : out std_logic;
tromflag0,tromflag1 : out std_logic;
tbufq : out std_logic_vector(19 downto 0);
tbuf_q : out std_logic_vector(19 downto 0);
tbd0,tbd1,tbd2,tbd3 : out std_logic_vector(4 downto 0);
ited : out std_logic_vector(19 downto 0);
outpri : out std_logic_vector(19 downto 0);
outflag : out std_logic;
saveflag,oena : out std_logic;
tloopq : out std_logic
);
END entity;
ARCHITECTURE rtl OF dec32 IS
signal Idata_t0,Qdata_t0 : std_logic_vector(4 downto 0);
signal Itemp0,Qtemp0 : std_logic_vector(4 downto 0);
signal fenat0,fenat1,fenat2,fenat3,fenat4 : std_logic;
signal fenat5,fenat6,fenat7,fenat8,fenat9 : std_logic;
signal fenat10,fenat11,fenat12,fenat13,fenat14 : std_logic;
signal fenat15,fenat16,fenat17,fenat18,fenat19 : std_logic;
signal fenat20,fenat21,fenat22,fenat23,fenat24 : std_logic;
signal fenat25,fenat26,fenat27,fenat28,fenat29 : std_logic;
signal hfena : std_logic;
signal count : std_logic_vector(7 downto 0);
signal ite_begin : std_logic;
signal ite_num : std_logic_vector(3 downto 0);
signal cnt0,cnt0_temp : std_logic_vector(3 downto 0);
signal cnt1 : std_logic_vector(4 downto 0);
signal we,we_shift0,we_shift1 : std_logic;
signal we_temp0,we_temp1,we_temp2,we_temp3 : std_logic;
signal we_temp4,we_temp5,we_temp6,we_temp7 : std_logic;
signal we_temp8,we_temp9,we_temp10,we_temp11 : std_logic;
signal we_temp12,we_temp13,we_temp14 : std_logic;
--=============================================
signal cnt7,cnt7_temp0,cnt7_temp1 : std_logic_vector(4 downto 0);
signal cnt8 : std_logic_vector(4 downto 0);
signal cnt8_temp : std_logic_vector(4 downto 0);
signal loopq : std_logic_vector(4 downto 0);
--==================================================
signal cnt2,cnt2_temp0,cnt2_temp1 : std_logic_vector(2 downto 0);
signal bufrad_t0,bufrad_t1 : std_logic_vector(8 downto 0);
signal bufre,bufret0,bufret1 : std_logic;
signal cnt3 : std_logic_vector(4 downto 0);
signal cnt3_temp : std_logic_vector(5 downto 0);
signal read_highbit : std_logic;
signal romflag0,romflag1,romf : std_logic;
signal rflag0_t0,rflag0_t1,rflag0_t2,rflag0_t3 : std_logic;
signal rflag1_t0,rflag1_t1,rflag1_t2,rflag1_t3 : std_logic;
signal bufq,buf_q : std_logic_vector(19 downto 0);
signal ite_b : std_logic;
--============================================
signal cnt4,cnt4_temp,cnt4_temp1 : std_logic_vector(2 downto 0);
signal cnt5,cnt5_temp : std_logic_vector(1 downto 0);
signal cnt6 : std_logic_vector(2 downto 0);
signal midbuf_sel : std_logic;
signal re0,re1,re2,re3 : std_logic;
--============================================
signal mdata0_temp,mdata1_temp : std_logic_vector(9 downto 0);
signal mdata2_temp,mdata3_temp : std_logic_vector(9 downto 0);
signal prid0_temp,prid1_temp : std_logic_vector(9 downto 0);
signal prid2_temp,prid3_temp : std_logic_vector(9 downto 0);
signal nd0,nd1,nd2,nd3 : std_logic_vector(9 downto 0);
signal nd0_temp,nd1_temp,nd2_temp,nd3_temp : std_logic_vector(9 downto 0);
signal onemark0,onemark1,onemark2,onemark3 : std_logic;
signal zeromark00,zeromark01 : std_logic;
signal zeromark0 : std_logic_vector(1 downto 0);
signal zeromark10,zeromark11 : std_logic;
signal zeromark1 : std_logic_vector(1 downto 0);
signal zeromark20,zeromark21 : std_logic;
signal zeromark2 : std_logic_vector(1 downto 0);
signal zeromark30,zeromark31 : std_logic;
signal zeromark3 : std_logic_vector(1 downto 0);
signal newd0,newd1,newd2,newd3 : std_logic_vector(4 downto 0);
signal midbufcol : std_logic_vector(2 downto 0);
signal midbufrow : std_logic_vector(5 downto 0);
signal midbufwe : std_logic;
signal itepri0,itepri1,itepri2,itepri3 : std_logic_vector(4 downto 0);
signal midpri,mid_pri : std_logic_vector(19 downto 0);
signal midq,mid_q : std_logic_vector(19 downto 0);
signal mq0,mq1,mq2,mq3 : std_logic_vector(19 downto 0);
signal mq4,mq5,mq6,mq7 : std_logic_vector(19 downto 0);
signal alpha : std_logic;
--=====================================================
component bufwe_shift IS
PORT(clk : in std_logic;
input : in std_logic;
output : out std_logic
);
END component;
component bufram IS
PORT
(
data : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
rdaddress : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
rdclock : IN STD_LOGIC ;
rden : IN STD_LOGIC := '1';
wraddress : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
wrclock : IN STD_LOGIC ;
wren : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (19 DOWNTO 0)
);
END component;
component shift_iteb IS
PORT
(
clk : in std_logic;
din : in std_logic;
dout : out std_logic
);
END component;
component add9 IS
PORT
(
dataa : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
clock : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
);
END component;
component shift_midw IS
PORT
(
clk : in std_logic;
incol : in std_logic_vector(2 downto 0);
inrow : in std_logic_vector(5 downto 0);
inwe : in std_logic;
outcol : out std_logic_vector(2 downto 0);
outrow : out std_logic_vector(5 downto 0);
outwe : out std_logic
);
END component;
component itepri_sft IS
PORT
(
clk : in std_logic;
indata : in std_logic_vector(4 downto 0);
outdata : out std_logic_vector(4 downto 0)
);
END component;
component midbuf IS
PORT
(
clk : in std_logic;
data0,data1,data2,data3 : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
wren : IN STD_LOGIC;
wradd : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rden0,rden1,rden2,rden3 : IN STD_LOGIC;
rdadd : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
sel : in std_logic;
--q0,q1,q2,q3 : OUT STD_LOGIC_VECTOR (19 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (19 DOWNTO 0)
);
END component;
component outstr_shift IS
PORT(clk : in std_logic;
input : in std_logic;
output : out std_logic;
output2 : out std_logic;
output3 : out std_logic
);
END component;
component loopram IS
PORT
(
data : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
rdaddress : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
rdclock : IN STD_LOGIC ;
rden : IN STD_LOGIC := '1';
wraddress : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
wrclock : IN STD_LOGIC ;
wren : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END component;
begin
process(clk)
begin
if clk'event and clk='1' then
fenat0<=framestart;
fenat1<=fenat0;
fenat2<=fenat1;
fenat3<=fenat2;
fenat4<=fenat3;
fenat5<=fenat4;
fenat6<=fenat5;
fenat7<=fenat6;
fenat8<=fenat7;
fenat9<=fenat8;
fenat10<=fenat9;
fenat11<=fenat10;
fenat12<=fenat11;
fenat13<=fenat12;
fenat14<=fenat13;
fenat15<=fenat14;
fenaout<=fenat13;
end if;
end process;
process(clk)
begin
if clk'event and clk='1' then
if fenat13='0' then
cnt0<="1011";
else
case cnt0 is
when "1011"=>cnt0<="0001";
when others =>cnt0<=cnt0+"0001";
end case;
end if;
cnt0_temp<=cnt0;
end if;
end process;
process(clk)
begin
if clk'event and clk='1' then
if fenat13='0' then
cnt1<="00001";
else
case cnt0 is
when "1011"=>case cnt1 is
--when "10111"=>cnt1<="00010";
when others=> cnt1<=cnt1+'1';
end case;
when others =>null;
end case;
end if;
tcnt0<=cnt0;--_temp;
tcnt1<=cnt1;
Itemp0<=Idata;
Qtemp0<=Qdata;
--Itemp1<=Itemp0;
--Qtemp1<=Qtemp0;
tI<=Itemp0;
tQ<=Qtemp0;
end if;
end process;
process(clk)
begin
if clk'event and clk='1' then
if fenat1='0' then
we<=not we;
end if;
we_temp0<=we;
we_temp1<=we_temp0;
we_temp2<=we_temp1;
we_temp3<=we_temp2;
we_temp4<=we_temp3;
we_temp5<=we_temp4;
we_temp6<=we_temp5;
we_temp7<=we_temp6;
we_temp8<=we_temp7;
we_temp9<=we_temp8;
we_temp10<=we_temp9;
we_temp11<=we_temp10;
we_temp12<=we_temp11;
we_temp13<=we_temp12;
twe<=we_temp12;--we;
we_shift1<=we_shift0;
tre<=we_shift1;
end if;
end process;
process(clk)
begin
if clk'event and clk='1' then
if fenat1='0' then
cnt7<="00010";
else
case cnt7 is
when "10001"=>cnt7<="00010";
when others=>cnt7<=cnt7+"00001";
end case;
end if;
cnt7_temp0<=cnt7;
cnt7_temp1<=cnt7_temp0;
--tcnt7<=cnt7_temp0;
end if;
end process;
process(clk)
begin
if clk'event and clk='1' then
if fenat1='0' then
cnt8<="00010";
else
case cnt7 is
when "10001"=>case cnt8 is
when "10001"=>cnt8<="00010";
when others=>cnt8<=cnt8+"00001";
end case;
when others=>null;
end case;
end if;
cnt8_temp<=cnt8;
--tcnt8<=we_shift1 & cnt8_temp;
end if;
end process;
dloopbuf:loopram
port map
(data=>Qtemp0 & Itemp0,
rdaddress=>we_shift1 & cnt8_temp & cnt7_temp0,
rdclock=>clk,
rden=>'1',
wraddress=>we_temp12 & cnt1 & cnt0,
wrclock=>clk,
wren=>'1',
q=>loopq
);
process(clk)
begin
if clk'event and clk='1' then
tloopq<=loopq(4);
end if;
end process;
--===============================
process(hclk)
begin
if hclk'event and hclk='1' then
hfena<=fenat3;
end if;
end process;
bufwes0: bufwe_shift PORT map(clk,we,we_shift0);
process(hclk)
begin
if hclk'event and hclk='1' then
--if fenat3='0' then
if hfena='0' then
count<="11010101";
else
case count is
when "11010101"=>count<="00000000";
when others=>count<=count+"00000001";
end case;
end if;
tcount<=count;
end if;
end process;
process(hclk)
begin
if hclk'event and hclk='1' then
case count is
when "00000000"=>ite_begin<='1';
when others=>ite_begin<='0';
end case;
tite_begin<=ite_begin;
t_ite_b<=ite_b;
end if;
end process;
shift_iteb0 : shift_iteb PORT MAP (hclk,ite_begin,ite_b);
process(hclk)
begin
if hclk'event and hclk='1' then
--if fenat3='0' then
if hfena='0' then
ite_num<="1111";
else
case ite_begin is
when '1'=>case ite_num is
when "1110"=>ite_num<="1110";
when others=>ite_num<=ite_num+'1';
end case;
when '0'=>null;
end case;
end if;
tite_num<=ite_num;
end if;
end process;
--===========================================
process(hclk)
begin
if hclk'event and hclk='1' then
case ite_num is
when "0000"=>
if ite_begin='1' then
cnt2<="101";
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