outstr_shift.vhd

完整的TPC编译码VHDL程序

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_SIGNED.ALL;
use ieee.std_logic_arith.all;
ENTITY outstr_shift IS
   PORT(clk              : in std_logic;
        input           : in std_logic;
        output          : out std_logic;
        output2         : out std_logic;
        output3         : out std_logic
	   );
END  outstr_shift;

ARCHITECTURE rtl OF outstr_shift IS
signal shift0,shift1,shift2,shift3              : std_logic;
signal temp0,temp1,temp2,temp3,temp4              : std_logic;
signal temp5,temp6,temp7,temp8,temp9              : std_logic;
signal temp10,temp11,temp12,temp13,temp14              : std_logic;
signal temp15,temp16,temp17,temp18,temp19              : std_logic;
signal temp20,temp21,temp22,temp23,temp24              : std_logic;
signal temp25,temp26,temp27,temp28,temp29              : std_logic;
signal temp30,temp31,temp32,temp33,temp34              : std_logic;
signal temp35,temp36,temp37,temp38,temp39              : std_logic;
signal temp40,temp41,temp42,temp43,temp44              : std_logic;
signal temp45,temp46,temp47,temp48,temp49              : std_logic;
signal temp50,temp51,temp52,temp53,temp54              : std_logic;
signal temp55,temp56,temp57,temp58,temp59              : std_logic;
signal tem0,tem1,tem2,tem3,tem4,tem5                   : std_logic;
signal t0,t1,t2,t3,t4,t5,t6                               : std_logic;

component shift IS
   PORT( clk              : in std_logic;
         input            : in std_logic;
         output           : out std_logic 
	   );
END  component;

begin

s0: shift port map(clk,input,temp0);
s1: shift port map(clk,temp0,temp1);
s2: shift port map(clk,temp1,temp2);
s3: shift port map(clk,temp2,temp3);
s4: shift port map(clk,temp3,temp4);
s5: shift port map(clk,temp4,temp5);
s6: shift port map(clk,temp5,temp6);
s7: shift port map(clk,temp6,temp7);
s8: shift port map(clk,temp7,temp8);
s9: shift port map(clk,temp8,temp9);
s10: shift port map(clk,temp9,temp10);
s11: shift port map(clk,temp10,temp11);
s12: shift port map(clk,temp11,temp12);
s13: shift port map(clk,temp12,temp13);
s14: shift port map(clk,temp13,temp14);
s15: shift port map(clk,temp14,temp15);
s16: shift port map(clk,temp15,temp16);
s17: shift port map(clk,temp16,temp17);
s18: shift port map(clk,temp17,temp18);
s19: shift port map(clk,temp18,temp19);
s20: shift port map(clk,temp19,temp20);
s21: shift port map(clk,temp20,temp21);
s22: shift port map(clk,temp21,temp22);
s23: shift port map(clk,temp22,temp23);
s24: shift port map(clk,temp23,temp24);
s25: shift port map(clk,temp24,temp25);
s26: shift port map(clk,temp25,temp26);
s27: shift port map(clk,temp26,temp27);
s28: shift port map(clk,temp27,temp28);
s29: shift port map(clk,temp28,temp29);
s30: shift port map(clk,temp29,temp30);
s31: shift port map(clk,temp30,temp31);
s32: shift port map(clk,temp31,temp32);
s33: shift port map(clk,temp32,temp33);
s34: shift port map(clk,temp33,temp34);
s35: shift port map(clk,temp34,temp35);
s36: shift port map(clk,temp35,temp36);
s37: shift port map(clk,temp36,temp37);
s38: shift port map(clk,temp37,temp38);
s39: shift port map(clk,temp38,temp39);
s40: shift port map(clk,temp39,temp40);
s41: shift port map(clk,temp40,temp41);
s42: shift port map(clk,temp41,temp42);
s43: shift port map(clk,temp42,temp43);
s44: shift port map(clk,temp43,temp44);
s45: shift port map(clk,temp44,temp45);
s46: shift port map(clk,temp45,temp46);
s47: shift port map(clk,temp46,temp47);
s48: shift port map(clk,temp47,temp48);
s49: shift port map(clk,temp48,temp49);
s50: shift port map(clk,temp49,temp50);
s51: shift port map(clk,temp50,temp51);
s52: shift port map(clk,temp51,temp52);

process(clk)
begin
    if clk'event and clk='1' then
       t0<=temp50;
       t1<=t0;
       t2<=t1;
       t3<=t2;
       t4<=t3;
       t5<=t4;
       t6<=t5;
       output<=not t1;

       tem0<=temp24;
       tem1<=tem0;
       tem2<=tem1;
       tem3<=tem2;
       tem4<=tem3;
       tem5<=tem4;

       output2<=not tem5;

       output3<=not t6;

    end if;
end process;



end rtl;