📄 s16_1.vhd
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-- megafunction wizard: %LPM_MUX%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_mux
-- ============================================================
-- File Name: s16_1.vhd
-- Megafunction Name(s):
-- lpm_mux
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 4.0 Build 190 1/28/2004 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2004 Altera Corporation
--Any megafunction design, and related netlist (encrypted or decrypted),
--support information, device programming or simulation file, and any other
--associated documentation or information provided by Altera or a partner
--under Altera's Megafunction Partnership Program may be used only
--to program PLD devices (but not masked PLD devices) from Altera. Any
--other use of such megafunction design, netlist, support information,
--device programming or simulation file, or any other related documentation
--or information is prohibited for any other purpose, including, but not
--limited to modification, reverse engineering, de-compiling, or use with
--any other silicon devices, unless such use is explicitly licensed under
--a separate agreement with Altera or a megafunction partner. Title to the
--intellectual property, including patents, copyrights, trademarks, trade
--secrets, or maskworks, embodied in any such megafunction design, netlist,
--support information, device programming or simulation file, or any other
--related documentation or information provided by Altera or a megafunction
--partner, remains with Altera, the megafunction partner, or their respective
--licensors. No other licenses, including any licenses needed under any third
--party's intellectual property, are provided herein.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
ENTITY s16_1 IS
PORT
(
clock : IN STD_LOGIC ;
data15x : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
data14x : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
data13x : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
data12x : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
data11x : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
data10x : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
data9x : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
data8x : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
data7x : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
data6x : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
data5x : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
data4x : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
data3x : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
data2x : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
data1x : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
data0x : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
sel : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END s16_1;
ARCHITECTURE SYN OF s16_1 IS
-- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC_2D (15 DOWNTO 0, 3 DOWNTO 0);
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL sub_wire7 : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL sub_wire8 : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL sub_wire9 : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL sub_wire10 : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL sub_wire11 : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL sub_wire12 : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL sub_wire13 : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL sub_wire14 : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL sub_wire15 : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL sub_wire16 : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL sub_wire17 : STD_LOGIC_VECTOR (3 DOWNTO 0);
COMPONENT lpm_mux
GENERIC (
lpm_pipeline : NATURAL;
lpm_size : NATURAL;
lpm_widths : NATURAL;
lpm_width : NATURAL;
lpm_type : STRING
);
PORT (
sel : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_2D (15 DOWNTO 0, 3 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(3 DOWNTO 0);
sub_wire1 <= data15x(3 DOWNTO 0);
sub_wire3 <= data14x(3 DOWNTO 0);
sub_wire4 <= data13x(3 DOWNTO 0);
sub_wire5 <= data12x(3 DOWNTO 0);
sub_wire6 <= data11x(3 DOWNTO 0);
sub_wire7 <= data10x(3 DOWNTO 0);
sub_wire8 <= data9x(3 DOWNTO 0);
sub_wire9 <= data8x(3 DOWNTO 0);
sub_wire10 <= data7x(3 DOWNTO 0);
sub_wire11 <= data6x(3 DOWNTO 0);
sub_wire12 <= data5x(3 DOWNTO 0);
sub_wire13 <= data4x(3 DOWNTO 0);
sub_wire14 <= data3x(3 DOWNTO 0);
sub_wire15 <= data2x(3 DOWNTO 0);
sub_wire16 <= data1x(3 DOWNTO 0);
sub_wire17 <= data0x(3 DOWNTO 0);
sub_wire2(15, 0) <= sub_wire1(0);
sub_wire2(15, 1) <= sub_wire1(1);
sub_wire2(15, 2) <= sub_wire1(2);
sub_wire2(15, 3) <= sub_wire1(3);
sub_wire2(14, 0) <= sub_wire3(0);
sub_wire2(14, 1) <= sub_wire3(1);
sub_wire2(14, 2) <= sub_wire3(2);
sub_wire2(14, 3) <= sub_wire3(3);
sub_wire2(13, 0) <= sub_wire4(0);
sub_wire2(13, 1) <= sub_wire4(1);
sub_wire2(13, 2) <= sub_wire4(2);
sub_wire2(13, 3) <= sub_wire4(3);
sub_wire2(12, 0) <= sub_wire5(0);
sub_wire2(12, 1) <= sub_wire5(1);
sub_wire2(12, 2) <= sub_wire5(2);
sub_wire2(12, 3) <= sub_wire5(3);
sub_wire2(11, 0) <= sub_wire6(0);
sub_wire2(11, 1) <= sub_wire6(1);
sub_wire2(11, 2) <= sub_wire6(2);
sub_wire2(11, 3) <= sub_wire6(3);
sub_wire2(10, 0) <= sub_wire7(0);
sub_wire2(10, 1) <= sub_wire7(1);
sub_wire2(10, 2) <= sub_wire7(2);
sub_wire2(10, 3) <= sub_wire7(3);
sub_wire2(9, 0) <= sub_wire8(0);
sub_wire2(9, 1) <= sub_wire8(1);
sub_wire2(9, 2) <= sub_wire8(2);
sub_wire2(9, 3) <= sub_wire8(3);
sub_wire2(8, 0) <= sub_wire9(0);
sub_wire2(8, 1) <= sub_wire9(1);
sub_wire2(8, 2) <= sub_wire9(2);
sub_wire2(8, 3) <= sub_wire9(3);
sub_wire2(7, 0) <= sub_wire10(0);
sub_wire2(7, 1) <= sub_wire10(1);
sub_wire2(7, 2) <= sub_wire10(2);
sub_wire2(7, 3) <= sub_wire10(3);
sub_wire2(6, 0) <= sub_wire11(0);
sub_wire2(6, 1) <= sub_wire11(1);
sub_wire2(6, 2) <= sub_wire11(2);
sub_wire2(6, 3) <= sub_wire11(3);
sub_wire2(5, 0) <= sub_wire12(0);
sub_wire2(5, 1) <= sub_wire12(1);
sub_wire2(5, 2) <= sub_wire12(2);
sub_wire2(5, 3) <= sub_wire12(3);
sub_wire2(4, 0) <= sub_wire13(0);
sub_wire2(4, 1) <= sub_wire13(1);
sub_wire2(4, 2) <= sub_wire13(2);
sub_wire2(4, 3) <= sub_wire13(3);
sub_wire2(3, 0) <= sub_wire14(0);
sub_wire2(3, 1) <= sub_wire14(1);
sub_wire2(3, 2) <= sub_wire14(2);
sub_wire2(3, 3) <= sub_wire14(3);
sub_wire2(2, 0) <= sub_wire15(0);
sub_wire2(2, 1) <= sub_wire15(1);
sub_wire2(2, 2) <= sub_wire15(2);
sub_wire2(2, 3) <= sub_wire15(3);
sub_wire2(1, 0) <= sub_wire16(0);
sub_wire2(1, 1) <= sub_wire16(1);
sub_wire2(1, 2) <= sub_wire16(2);
sub_wire2(1, 3) <= sub_wire16(3);
sub_wire2(0, 0) <= sub_wire17(0);
sub_wire2(0, 1) <= sub_wire17(1);
sub_wire2(0, 2) <= sub_wire17(2);
sub_wire2(0, 3) <= sub_wire17(3);
lpm_mux_component : lpm_mux
GENERIC MAP (
lpm_pipeline => 1,
lpm_size => 16,
lpm_widths => 4,
lpm_width => 4,
lpm_type => "LPM_MUX"
)
PORT MAP (
sel => sel,
clock => clock,
data => sub_wire2,
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: MEGAFN_PORT_INFO_0 STRING "data;sel;clock;aclr;clken"
-- Retrieval info: PRIVATE: MEGAFN_PORT_INFO_1 STRING "result"
-- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "16"
-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "4"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "4"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: result 0 0 4 0 OUTPUT NODEFVAL result[3..0]
-- Retrieval info: USED_PORT: data15x 0 0 4 0 INPUT NODEFVAL data15x[3..0]
-- Retrieval info: USED_PORT: data14x 0 0 4 0 INPUT NODEFVAL data14x[3..0]
-- Retrieval info: USED_PORT: data13x 0 0 4 0 INPUT NODEFVAL data13x[3..0]
-- Retrieval info: USED_PORT: data12x 0 0 4 0 INPUT NODEFVAL data12x[3..0]
-- Retrieval info: USED_PORT: data11x 0 0 4 0 INPUT NODEFVAL data11x[3..0]
-- Retrieval info: USED_PORT: data10x 0 0 4 0 INPUT NODEFVAL data10x[3..0]
-- Retrieval info: USED_PORT: data9x 0 0 4 0 INPUT NODEFVAL data9x[3..0]
-- Retrieval info: USED_PORT: data8x 0 0 4 0 INPUT NODEFVAL data8x[3..0]
-- Retrieval info: USED_PORT: data7x 0 0 4 0 INPUT NODEFVAL data7x[3..0]
-- Retrieval info: USED_PORT: data6x 0 0 4 0 INPUT NODEFVAL data6x[3..0]
-- Retrieval info: USED_PORT: data5x 0 0 4 0 INPUT NODEFVAL data5x[3..0]
-- Retrieval info: USED_PORT: data4x 0 0 4 0 INPUT NODEFVAL data4x[3..0]
-- Retrieval info: USED_PORT: data3x 0 0 4 0 INPUT NODEFVAL data3x[3..0]
-- Retrieval info: USED_PORT: data2x 0 0 4 0 INPUT NODEFVAL data2x[3..0]
-- Retrieval info: USED_PORT: data1x 0 0 4 0 INPUT NODEFVAL data1x[3..0]
-- Retrieval info: USED_PORT: data0x 0 0 4 0 INPUT NODEFVAL data0x[3..0]
-- Retrieval info: USED_PORT: sel 0 0 4 0 INPUT NODEFVAL sel[3..0]
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: result 0 0 4 0 @result 0 0 4 0
-- Retrieval info: CONNECT: @data 1 15 4 0 data15x 0 0 4 0
-- Retrieval info: CONNECT: @data 1 14 4 0 data14x 0 0 4 0
-- Retrieval info: CONNECT: @data 1 13 4 0 data13x 0 0 4 0
-- Retrieval info: CONNECT: @data 1 12 4 0 data12x 0 0 4 0
-- Retrieval info: CONNECT: @data 1 11 4 0 data11x 0 0 4 0
-- Retrieval info: CONNECT: @data 1 10 4 0 data10x 0 0 4 0
-- Retrieval info: CONNECT: @data 1 9 4 0 data9x 0 0 4 0
-- Retrieval info: CONNECT: @data 1 8 4 0 data8x 0 0 4 0
-- Retrieval info: CONNECT: @data 1 7 4 0 data7x 0 0 4 0
-- Retrieval info: CONNECT: @data 1 6 4 0 data6x 0 0 4 0
-- Retrieval info: CONNECT: @data 1 5 4 0 data5x 0 0 4 0
-- Retrieval info: CONNECT: @data 1 4 4 0 data4x 0 0 4 0
-- Retrieval info: CONNECT: @data 1 3 4 0 data3x 0 0 4 0
-- Retrieval info: CONNECT: @data 1 2 4 0 data2x 0 0 4 0
-- Retrieval info: CONNECT: @data 1 1 4 0 data1x 0 0 4 0
-- Retrieval info: CONNECT: @data 1 0 4 0 data0x 0 0 4 0
-- Retrieval info: CONNECT: @sel 0 0 4 0 sel 0 0 4 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL s16_1.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL s16_1.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL s16_1.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL s16_1.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL s16_1_inst.vhd TRUE
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