gen_tseq.vhd

完整的TPC编译码VHDL程序

LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

ENTITY gen_tseq IS
	PORT
	(
  clk		                         : in   std_logic;
  lcol0,lcol1,lcol2,lcol3            : in   std_logic_vector(2 downto 0);
  lnum0,lnum1,lnum2,lnum3            : in   std_logic_vector(1 downto 0);
  hardin                             : in   std_logic_vector(3 downto 0);
  hcol                               : in   std_logic_vector(2 downto 0);
  
  seq0,seq1,seq2,seq3                : out std_logic_vector(3 downto 0);
  seq4,seq5,seq6,seq7                : out std_logic_vector(3 downto 0);
  seq8,seq9,seq10,seq11              : out std_logic_vector(3 downto 0);
  seq12,seq13,seq14,seq15            : out std_logic_vector(3 downto 0)

	);
END entity;
ARCHITECTURE rtl OF gen_tseq IS
signal   hcolad0,hcolad1,hcolad2,hcolad3                 : std_logic_vector(4 downto 0);
signal   lcolad0,lcolad1,lcolad2,lcolad3                 : std_logic_vector(4 downto 0);
signal   comresult0,comresult1                           : std_logic_vector(3 downto 0);
signal   comresult2,comresult3                           : std_logic_vector(3 downto 0);
signal   hardtemp0, hardtemp1                            : std_logic_vector(3 downto 0);
signal   s0,s1,s2,s3,s4,s5,s6,s7                         : std_logic_vector(3 downto 0);
signal   s8,s9,s10,s11,s12,s13,s14,s15                   : std_logic_vector(3 downto 0);

begin

process(clk)
begin
   if clk'event and clk='1' then
     hcolad0<=hcol & "00";
     hcolad1<=hcol & "01";
     hcolad2<=hcol & "10";
     hcolad3<=hcol & "11";

     lcolad0<=lcol0 & lnum0;
     lcolad1<=lcol1 & lnum1;
     lcolad2<=lcol2 & lnum2;
     lcolad3<=lcol3 & lnum3;

     hardtemp0<=hardin;
     hardtemp1<=hardtemp0;
   end if;
end process;

process(clk)
begin
   if clk'event and clk='1' then
     --======================
     if hcolad0=lcolad0 then
        comresult0(0)<='1';
     else
        comresult0(0)<='0';
     end if; 
     if hcolad0=lcolad1 then
        comresult0(1)<='1';
     else
        comresult0(1)<='0';
     end if; 
     if hcolad0=lcolad2 then
        comresult0(2)<='1';
     else
        comresult0(2)<='0';
     end if; 
     if hcolad0=lcolad3 then
        comresult0(3)<='1';
     else
        comresult0(3)<='0';
     end if;
     --======================
     if hcolad1=lcolad0 then
        comresult1(0)<='1';
     else
        comresult1(0)<='0';
     end if; 
     if hcolad1=lcolad1 then
        comresult1(1)<='1';
     else
        comresult1(1)<='0';
     end if; 
     if hcolad1=lcolad2 then
        comresult1(2)<='1';
     else
        comresult1(2)<='0';
     end if; 
     if hcolad1=lcolad3 then
        comresult1(3)<='1';
     else
        comresult1(3)<='0';
     end if;
     --=======================
     if hcolad2=lcolad0 then
        comresult2(0)<='1';
     else
        comresult2(0)<='0';
     end if; 
     if hcolad2=lcolad1 then
        comresult2(1)<='1';
     else
        comresult2(1)<='0';
     end if; 
     if hcolad2=lcolad2 then
        comresult2(2)<='1';
     else
        comresult2(2)<='0';
     end if; 
     if hcolad2=lcolad3 then
        comresult2(3)<='1';
     else
        comresult2(3)<='0';
     end if;
     --=======================
     if hcolad3=lcolad0 then
        comresult3(0)<='1';
     else
        comresult3(0)<='0';
     end if; 
     if hcolad3=lcolad1 then
        comresult3(1)<='1';
     else
        comresult3(1)<='0';
     end if; 
     if hcolad3=lcolad2 then
        comresult3(2)<='1';
     else
        comresult3(2)<='0';
     end if; 
     if hcolad3=lcolad3 then
        comresult3(3)<='1';
     else
        comresult3(3)<='0';
     end if;
   end if;
end process;
--==============================================
process(clk)
begin
   if clk'event and clk='1' then
       case comresult0 is
          when "1000"=>s0(0)<=hardtemp1(0);
                       s1(0)<=not hardtemp1(0);
                       s2(0)<=not hardtemp1(0);
                       s3(0)<= hardtemp1(0);
                       s4(0)<= hardtemp1(0);
                       s5(0)<=not hardtemp1(0);
                       s6(0)<=not hardtemp1(0);
                       s7(0)<= hardtemp1(0);
                       s8(0)<= hardtemp1(0);
                       s9(0)<=not hardtemp1(0);
                       s10(0)<=not hardtemp1(0);
                       s11(0)<=hardtemp1(0);
                       s12(0)<= hardtemp1(0);
                       s13(0)<=not hardtemp1(0);
                       s14(0)<=not hardtemp1(0);
                       s15(0)<= hardtemp1(0);
          when "0100"=>s0(0)<=hardtemp1(0);
                       s1(0)<=hardtemp1(0);
                       s2(0)<=not hardtemp1(0);
                       s3(0)<=not hardtemp1(0);
                       s4(0)<=not hardtemp1(0);
                       s5(0)<=not hardtemp1(0);
                       s6(0)<=hardtemp1(0);
                       s7(0)<=hardtemp1(0);
                       s8(0)<=hardtemp1(0);
                       s9(0)<=hardtemp1(0);
                       s10(0)<=not hardtemp1(0);
                       s11(0)<=not hardtemp1(0);
                       s12(0)<=not  hardtemp1(0);
                       s13(0)<=not hardtemp1(0);
                       s14(0)<=hardtemp1(0);
                       s15(0)<= hardtemp1(0);

          when "0010"=>s0(0)<=hardtemp1(0);
                       s1(0)<=hardtemp1(0);
                       s2(0)<=hardtemp1(0);
                       s3(0)<=hardtemp1(0);
                       s4(0)<=not hardtemp1(0);
                       s5(0)<=not hardtemp1(0);
                       s6(0)<=not hardtemp1(0);
                       s7(0)<=not hardtemp1(0);
                       s8(0)<=not hardtemp1(0);
                       s9(0)<=not hardtemp1(0);
                       s10(0)<=not hardtemp1(0);
                       s11(0)<=not hardtemp1(0);
                       s12(0)<=hardtemp1(0);
                       s13(0)<=hardtemp1(0);
                       s14(0)<=hardtemp1(0);
                       s15(0)<=hardtemp1(0);
          when "0001"=>s0(0)<=hardtemp1(0);
                       s1(0)<=hardtemp1(0);
                       s2(0)<=hardtemp1(0);
                       s3(0)<=hardtemp1(0);
                       s4(0)<=hardtemp1(0);
                       s5(0)<=hardtemp1(0);
                       s6(0)<=hardtemp1(0);
                       s7(0)<=hardtemp1(0);
                       s8(0)<=not hardtemp1(0);
                       s9(0)<=not hardtemp1(0);
                       s10(0)<=not hardtemp1(0);
                       s11(0)<=not hardtemp1(0);
                       s12(0)<=not hardtemp1(0);
                       s13(0)<=not hardtemp1(0);
                       s14(0)<=not hardtemp1(0);
                       s15(0)<=not hardtemp1(0);
          when others=>s0(0)<=hardtemp1(0);
                       s1(0)<=hardtemp1(0);
                       s2(0)<=hardtemp1(0);
                       s3(0)<=hardtemp1(0);
                       s4(0)<=hardtemp1(0);
                       s5(0)<=hardtemp1(0);
                       s6(0)<=hardtemp1(0);
                       s7(0)<=hardtemp1(0);
                       s8(0)<=hardtemp1(0);
                       s9(0)<=hardtemp1(0);
                       s10(0)<=hardtemp1(0);
                       s11(0)<=hardtemp1(0);
                       s12(0)<=hardtemp1(0);
                       s13(0)<=hardtemp1(0);
                       s14(0)<=hardtemp1(0);
                       s15(0)<=hardtemp1(0);
          end case;
--   end if;
--end process;

-----------------------------
--process(clk)
--begin
--   if clk'event and clk='1' then
       case comresult1 is
          when "1000"=>s0(1)<=hardtemp1(1);
                       s1(1)<=not hardtemp1(1);
                       s2(1)<=not hardtemp1(1);
                       s3(1)<= hardtemp1(1);
                       s4(1)<= hardtemp1(1);
                       s5(1)<=not hardtemp1(1);
                       s6(1)<=not hardtemp1(1);
                       s7(1)<= hardtemp1(1);
                       s8(1)<= hardtemp1(1);
                       s9(1)<=not hardtemp1(1);
                       s10(1)<=not hardtemp1(1);
                       s11(1)<=hardtemp1(1);
                       s12(1)<= hardtemp1(1);
                       s13(1)<=not hardtemp1(1);
                       s14(1)<=not hardtemp1(1);
                       s15(1)<= hardtemp1(1);
          when "0100"=>s0(1)<=hardtemp1(1);
                       s1(1)<=hardtemp1(1);
                       s2(1)<=not hardtemp1(1);
                       s3(1)<=not hardtemp1(1);
                       s4(1)<=not hardtemp1(1);
                       s5(1)<=not hardtemp1(1);
                       s6(1)<=hardtemp1(1);
                       s7(1)<=hardtemp1(1);
                       s8(1)<=hardtemp1(1);
                       s9(1)<=hardtemp1(1);
                       s10(1)<=not hardtemp1(1);