shift_midw.vhd

完整的TPC编译码VHDL程序

LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

ENTITY shift_midw IS
	PORT
	(
		clk		         : in   std_logic;
	 incol         : in   std_logic_vector(2 downto 0);
	 inrow         : in   std_logic_vector(5 downto 0);
  inwe          : in   std_logic;
  outcol        : out  std_logic_vector(2 downto 0);
  outrow        : out  std_logic_vector(5 downto 0);
  outwe         : out  std_logic
	);
END entity;
ARCHITECTURE rtl OF shift_midw IS
signal shfcol0,shfcol1,shfcol2,shfcol3,shfcol4,shfcol5   : std_logic_vector(2 downto 0);
signal shfrow0,shfrow1,shfrow2,shfrow3,shfrow4,shfrow5   : std_logic_vector(5 downto 0);
signal shfwe0,shfwe1,shfwe2,shfwe3,shfwe4,shfwe5         : std_logic;

begin
 process(clk)
 begin
   if clk'event and clk='1' then
    shfcol0<=incol;
    shfcol1<=shfcol0;
    shfcol2<=shfcol1;
    --shfcol3<=shfcol2;
    --shfcol4<=shfcol3;
    --shfcol5<=shfcol4;
    --shfcol6<=shfcol5;
    --shfcol7<=shfcol6;

    outcol<=shfcol2;

    shfrow0<=inrow;
    shfrow1<=shfrow0;
    shfrow2<=shfrow1;
    --shfrow3<=shfrow2;
    --shfrow4<=shfrow3;
    --shfrow5<=shfrow4;
    --shfrow6<=shfrow5;
    --shfrow7<=shfrow6;

    outrow<=shfrow2;

    shfwe0<=inwe;
    shfwe1<=shfwe0;
    shfwe2<=shfwe1;
    --shfwe3<=shfwe2;
    --shfwe4<=shfwe3;
    --shfwe5<=shfwe4;
    --shfwe6<=shfwe5;
    --shfwe7<=shfwe6;

    outwe<=shfwe2;


   end if;
 end process;

end rtl;