shiftseq.vhd

完整的TPC编译码VHDL程序

LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

ENTITY shiftseq IS
	PORT
	(
		clk		         : in   std_logic;
	 indata        : in   std_logic_vector(3 downto 0);
  outdata       : out  std_logic_vector(3 downto 0)

	);
END entity;
ARCHITECTURE rtl OF shiftseq IS
signal shf0,shf1,shf2,shf3,shf4,shf5,shf6,shf7           : std_logic_vector(3 downto 0);

begin
 process(clk)
 begin
   if clk'event and clk='1' then
    shf0<=indata;
    shf1<=shf0;
    shf2<=shf1;
    shf3<=shf2;
    shf4<=shf3;
    shf5<=shf4;
    shf6<=shf5;
    shf7<=shf6;



    outdata<=shf7;
   end if;
 end process;

end rtl;