shift_set.vhd

完整的TPC编译码VHDL程序

LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

ENTITY shift_set IS
	PORT
	(
		clk		         : in   std_logic;
	 indata        : in   std_logic;
  outdata       : out  std_logic
	);
END entity;
ARCHITECTURE rtl OF shift_set IS
signal shf0,shf1,shf2,shf3,shf4,shf5,shf6,shf7,shf8,shf9            : std_logic;
signal shf10,shf11,shf12,shf13,shf14,shf15,shf16,shf17,shf18,shf19  : std_logic;
signal shf20,shf21,shf22,shf23,shf24,shf25,shf26,shf27,shf28,shf29  : std_logic;
signal shf30,shf31,shf32,shf33,shf34,shf35,shf36,shf37,shf38,shf39  : std_logic;
signal shf40,shf41,shf42,shf43,shf44,shf45,shf46,shf47,shf48,shf49  : std_logic;

begin
 process(clk)
 begin
   if clk'event and clk='1' then
    shf0<=indata;
    shf1<=shf0;
    shf2<=shf1;
    shf3<=shf2;
    shf4<=shf3;
    shf5<=shf4;
    shf6<=shf5;
    shf7<=shf6;
    shf8<=shf7;
    shf9<=shf8;
    shf10<=shf9;
    shf11<=shf10;
    shf12<=shf11;
    shf13<=shf12;
    shf14<=shf13;
    shf15<=shf14;
    shf16<=shf15;
    shf17<=shf16;
    shf18<=shf17;
    shf19<=shf18;
    shf20<=shf19;

    shf21<=shf20;
    shf22<=shf21;
    shf23<=shf22;
    shf24<=shf23;
    shf25<=shf24;
    shf26<=shf25;
    shf27<=shf26;
    shf28<=shf27;
    shf29<=shf28;
    shf30<=shf29;

    shf31<=shf30;
    shf32<=shf31;
    shf33<=shf32;
    shf34<=shf33;
    shf35<=shf34;
    shf36<=shf35;
    shf37<=shf36;
    shf38<=shf37;
    shf39<=shf38;
    shf40<=shf39;

    shf41<=shf40;
    shf42<=shf41;
    shf43<=shf42;
    shf44<=shf43;
    shf45<=shf44;
    shf46<=shf45;
    shf47<=shf46;
    shf48<=shf47;



    outdata<=shf48;


   end if;
 end process;

end rtl;