correct.vhd

完整的TPC编译码VHDL程序

LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

ENTITY correct IS
PORT
( clk		                        : in  std_logic;
  seq                               : in  std_logic_vector(3 downto 0);
  seq_col                           : in  std_logic_vector(2 downto 0);
  re                                : in  std_logic_vector(6 downto 0);
  p_of_word                         : in  std_logic;
  cor_seq                           : out std_logic_vector(3 downto 0)
	);
END entity;
ARCHITECTURE rtl OF correct  IS
signal  bit_num0,bit_num1,bit_num2,bit_num3            : std_logic_vector(4 downto 0);
signal  seq_temp                                       : std_logic_vector(3 downto 0);
signal  re_temp                                        : std_logic_vector(4 downto 0);
signal  seq_va                                         : std_logic_vector(1 downto 0);
signal  seq_col_dly                                    : std_logic_vector(2 downto 0);
signal  newparity                                      : std_logic;

begin

process(clk)
begin
   if clk'event and clk='1' then
      bit_num0<=seq_col & "00";
      bit_num1<=seq_col & "01";
      bit_num2<=seq_col & "10";
      bit_num3<=seq_col & "11";
      
      seq_col_dly<=seq_col;
      newparity<=p_of_word;

      seq_temp<=seq;
      re_temp<=re(4 downto 0);
      seq_va<=re(6 downto 5);
   end if;
end process;

process(clk)
begin
   if clk'event and clk='1' then
       case seq_va is
           when "11"=>if re_temp=bit_num0 then
                        cor_seq(0)<=not seq_temp(0);
                      else
                        cor_seq(0)<=seq_temp(0);
                      end if;
                      if re_temp=bit_num1 then
                        cor_seq(1)<=not seq_temp(1);
                      else
                        cor_seq(1)<=seq_temp(1);
                      end if;
                      if re_temp=bit_num2 then
                        cor_seq(2)<=not seq_temp(2);
                      else
                        cor_seq(2)<=seq_temp(2);
                      end if;
                      
                      case seq_col_dly is
                         when "101"=>cor_seq(3)<=newparity;
                         when others=> if re_temp=bit_num3 then
                                          cor_seq(3)<=not seq_temp(3);
                                       else
                                          cor_seq(3)<=seq_temp(3);
                                       end if;
                      end case;
          when others=>case seq_col_dly is
                         when "101"=>cor_seq(3)<=newparity; 
                                     cor_seq(2 downto 0)<=seq_temp(2 downto 0);
                         when others=>cor_seq<=seq_temp; 
                       end case;
       end case; 
   end if;
end process;

end rtl;