cor16.vhd

完整的TPC编译码VHDL程序

LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

ENTITY cor16 IS
PORT
( clk		                              : in  std_logic;
  s0,s1,s2,s3,s4,s5                  : in  std_logic_vector(3 downto 0);
  s6,s7,s8,s9,s10                    : in  std_logic_vector(3 downto 0);
  s11,s12,s13,s14,s15                : in  std_logic_vector(3 downto 0);

  seq_col                            : in  std_logic_vector(2 downto 0);

  re0,re1,re2,re3,re4,re5            : in  std_logic_vector(6 downto 0);
  re6,re7,re8,re9,re10,re11          : in  std_logic_vector(6 downto 0);
  re12,re13,re14,re15                : in  std_logic_vector(6 downto 0);

  p0,p1,p2,p3,p4,p5,p6,p7            : in  std_logic;
  p8,p9,pa,pb,pc,pd,pe,pf            : in  std_logic;
 
  cq0,cq1,cq2,cq3,cq4,cq5            : out std_logic_vector(3 downto 0);
  cq6,cq7,cq8,cq9,cq10,cq11          : out std_logic_vector(3 downto 0);
  cq12,cq13,cq14,cq15                : out std_logic_vector(3 downto 0)

	);
END entity;
ARCHITECTURE rtl OF cor16  IS

component correct IS
	PORT
	(
		clk		                             : in  std_logic;
  seq                               : in  std_logic_vector(3 downto 0);
  seq_col                           : in  std_logic_vector(2 downto 0);
  re                                : in  std_logic_vector(6 downto 0);
  p_of_word                         : in  std_logic;
  cor_seq                           : out std_logic_vector(3 downto 0)

	);
END component;

begin

correct0: correct
port map
(
 	clk,
  s0,
  seq_col,
  re0,
  p0,
  cq0
	);

correct1: correct
port map
(
 	clk,
  s1,
  seq_col,
  re1,
  p1,
  cq1
	);
correct2: correct
port map
(
 	clk,
  s2,
  seq_col,
  re2,
  p2,
  cq2
	);
correct3: correct
port map
(
 	clk,
  s3,
  seq_col,
  re3,
  p3,
  cq3
	);
correct4: correct
port map
(
 	clk,
  s4,
  seq_col,
  re4,
  p4,
  cq4
	);
correct5: correct
port map
(
 	clk,
  s5,
  seq_col,
  re5,
  p5,
  cq5
	);
correct6: correct
port map
(
 	clk,
  s6,
  seq_col,
  re6,
  p6,
  cq6
	);
correct7: correct
port map
(
 	clk,
  s7,
  seq_col,
  re7,
  p7,
  cq7
	);
correct8: correct
port map
(
 	clk,
  s8,
  seq_col,
  re8,
  p8,
  cq8
	);
correct9: correct
port map
(
 	clk,
  s9,
  seq_col,
  re9,
  p9,
  cq9
	);
correct10: correct
port map
(
 	clk,
  s10,
  seq_col,
  re10,
  pa,
  cq10
	);
correct11: correct
port map
(
 	clk,
  s11,
  seq_col,
  re11,
  pb,
  cq11
	);
correct12: correct
port map
(
 	clk,
  s12,
  seq_col,
  re12,
  pc,
  cq12
	);
correct13: correct
port map
(
 	clk,
  s13,
  seq_col,
  re13,
  pd,
  cq13
	);
correct14: correct
port map
(
 	clk,
  s14,
  seq_col,
  re14,
  pe,
  cq14
	);
correct15: correct
port map
(
 	clk,
  s15,
  seq_col,
  re15,
  pf,
  cq15
	);


end rtl;