midbuf.vhd

来自「完整的TPC编译码VHDL程序」· VHDL 代码 · 共 233 行

LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

ENTITY midbuf IS
	PORT
	(
		clk		                              : in  std_logic;
  data0,data1,data2,data3		          : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
  wren                            		 : IN STD_LOGIC;
		wradd    	                        	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
  rden0,rden1,rden2,rden3            : IN STD_LOGIC;
		rdadd    		                        : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
  sel                                : in std_logic;
  --q0,q1,q2,q3                      		: OUT STD_LOGIC_VECTOR (19 DOWNTO 0);
  q                                  : OUT STD_LOGIC_VECTOR (19 DOWNTO 0)
	);
END entity;

ARCHITECTURE rtl OF midbuf IS

signal rden00,rden01,rden02,rden03                              : std_logic;
signal rden10,rden11,rden12,rden13                              : std_logic;
signal q00,q01,q02,q03                                          : std_logic_vector(19 downto 0);
signal q10,q11,q12,q13                                          : std_logic_vector(19 downto 0);
signal sel_temp0,sel_temp1                                      : std_logic;
signal rdaddress                                                : STD_LOGIC_VECTOR (5 DOWNTO 0);
signal wraddress	                                              	: STD_LOGIC_VECTOR (7 DOWNTO 0);
signal q_sel,q_sel_temp0,q_sel_temp1                            : STD_LOGIC_VECTOR (3 DOWNTO 0);
signal wren0,wren1                                              : std_logic;
signal d0,d1,d2,d3                                              : STD_LOGIC_VECTOR (4 DOWNTO 0);

component midram IS
	PORT
	(
		data		: IN STD_LOGIC_VECTOR (4 DOWNTO 0);
		wren		: IN STD_LOGIC  := '1';
		wraddress		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		rdaddress		: IN STD_LOGIC_VECTOR (5 DOWNTO 0);
		rden		: IN STD_LOGIC  := '1';
		wrclock		: IN STD_LOGIC ;
		rdclock		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (19 DOWNTO 0)
	);
END component;

          
begin

process(clk)
begin
  if clk'event and clk='1' then
     case sel is
         when '0'=>rden00<=rden0;
                   rden01<=rden1;
                   rden02<=rden2;
                   rden03<=rden3;

                   rden10<='0';
                   rden11<='0';
                   rden12<='0';
                   rden13<='0';

                   wren0<='0';
                   wren1<='1';

         when '1'=>rden00<='0';
                   rden01<='0';
                   rden02<='0';
                   rden03<='0';

                   rden10<=rden0;
                   rden11<=rden1;
                   rden12<=rden2;
                   rden13<=rden3;

                   wren0<='1';
                   wren1<='0';

     end case;
          rdaddress<=rdadd; 
          sel_temp0<=sel;
          sel_temp1<=sel_temp0;

          q_sel<=rden0 & rden1 & rden2 & rden3;
          q_sel_temp0<=q_sel;
          q_sel_temp1<=q_sel_temp0;

          d0<=data0;
          d1<=data1;
          d2<=data2;
          d3<=data3;

          wraddress<=wradd;
  end if;
end process;


process(clk)
begin
  if clk'event and clk='1' then
     case sel_temp1 is
         when '0'=>case q_sel_temp1 is--q_sel_temp0
                        when "1000"=>q<=q00;
                        when "0100"=>q<=q01;
                        when "0010"=>q<=q02;
                        when "0001"=>q<=q03;
                        when others=> null;
                   end case;              
         when '1'=>case q_sel_temp1 is
                        when "1000"=>q<=q10;
                        when "0100"=>q<=q11;
                        when "0010"=>q<=q12;
                        when "0001"=>q<=q13;
                        when others=> null;
                   end case;              
     end case;
     --q0<=q00;
     --q1<=q01;
     --q2<=q02;
     --q3<=q03;
  end if;
end process;


midram00: midram 
	PORT MAP
	(
		d0,
		wren0,
		wraddress,
		rdaddress,
		rden00,
		clk,
		clk,
		q00
	);

midram01: midram 
	PORT MAP
	(
		d1,
		wren0,
		wraddress,
		rdaddress,
		rden01,
		clk,
		clk,
		q01
	);

midram02: midram 
	PORT MAP
	(
		d2,
		wren0,
		wraddress,
		rdaddress,
		rden02,
		clk,
		clk,
		q02
	);

midram03: midram 
	PORT MAP
	(
		d3,
		wren0,
		wraddress,
		rdaddress,
		rden03,
		clk,
		clk,
		q03
	);


midram10: midram 
	PORT MAP
	(
		d0,
		wren1,
		wraddress,
		rdaddress,
		rden10,
		clk,
		clk,
		q10
	);

midram11: midram 
	PORT MAP
	(
		d1,
		wren1,
		wraddress,
		rdaddress,
		rden11,
		clk,
		clk,
		q11
	);

midram12: midram 
	PORT MAP
	(
		d2,
		wren1,
		wraddress,
		rdaddress,
		rden12,
		clk,
		clk,
		q12
	);

midram13: midram 
	PORT MAP
	(
		d3,
		wren1,
		wraddress,
		rdaddress,
		rden13,
		clk,
		clk,
		q13
	);


end rtl;