📄 frame_process.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
entity frame_process is
port(
reset :in std_logic;
symbol_clk :in std_logic; --符号时钟
--mode :in std_logic_vector(1 downto 0);
data_in_i :in std_logic_vector(4 downto 0); --i路数据
data_in_q :in std_logic_vector(4 downto 0); --q路数据
--temp1_i :out std_logic_vector(8 downto 0);
--temp2_i :out std_logic_vector(8 downto 0);
--temp1_q :out std_logic_vector(8 downto 0);
--temp2_q :out std_logic_vector(8 downto 0);
data_out_i :out std_logic_vector(4 downto 0); --i
data_out_q :out std_logic_vector(4 downto 0); --q
frame_pulse :out std_logic; --帧脉冲，负脉冲，上升沿对应着巴克码第1bit前沿
symbol_out :out std_logic;
frame_syn :out std_logic --帧同步标志
);
end entity;
architecture bh of frame_process is
component frame_dual_ram
PORT
(
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
rdaddress : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wraddress : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wren : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
END component;
constant th1 :integer:=40;
constant th2 :integer:=13;
type data1 is array (0 to 13) of std_logic_vector(9 downto 0);
signal frame_reg1 :data1;
signal frame_reg2 :data1;
signal ram_in :std_logic_vector(9 downto 0);
signal ram_out :std_logic_vector(9 downto 0);
signal wr_cnt :integer range 0 to 255;
signal rd_cnt :integer range 0 to 255;
type data4 is array (0 to 7) of std_logic_vector(1 downto 0);
--signal data_in_i :std_logic_vector(4 downto 0); --i路数据
--signal data_in_q :std_logic_vector(4 downto 0); --q路数据
signal tmp_data_out_i :std_logic_vector(4 downto 0); --i路数据
signal tmp_data_out_q :std_logic_vector(4 downto 0); --q路数据
type data2 is array (0 to 12) of std_logic_vector(4 downto 0);
constant bakema :std_logic_vector(10 downto 0) :="11100010010";----"0110010100110";--
begin
-----------------------------------------------
comp: frame_dual_ram
PORT map
(
clock =>symbol_clk,
data =>"000000" & ram_in,
rdaddress =>conv_std_logic_vector(rd_cnt,8),
wraddress =>conv_std_logic_vector(wr_cnt,8),
wren =>'1',
q(9 downto 0) =>ram_out
);
-------------------------------------------------------------
process(symbol_clk,reset)
variable frame_find :std_logic;
variable phase_flag :std_logic;
variable phase_flag1:std_logic;
variable phase1 :std_logic_vector(1 downto 0);
variable phase :data4;
variable tmp1_i :data2;
variable tmp1_q :data2;
variable tmp2_i :data2;
variable tmp2_q :data2;
variable sum1_i :std_logic_vector(8 downto 0);
variable sum1_q :std_logic_vector(8 downto 0);
variable sum2_i :std_logic_vector(8 downto 0);
variable sum2_q :std_logic_vector(8 downto 0);
variable count1 :integer range 0 to 511;
variable asyn_cnt1 :integer range 0 to 511;
variable asyn_cnt2 :integer range 0 to 511;
variable rd_ena :std_logic;
variable cnt :integer range 0 to 7;
variable tmp_sum :std_logic_vector(7 downto 0);
begin
if reset='0' then
wr_cnt <=0;
rd_cnt <=0;
asyn_cnt1 :=0;
asyn_cnt2 :=0;
frame_find :='0';
phase1 :="00";
count1 :=0;
frame_pulse <='1';
frame_syn <='0';
rd_ena :='0';
for i in 0 to 13 loop
frame_reg1(i)<=conv_std_logic_vector(0,10);
frame_reg2(i)<=conv_std_logic_vector(0,10);
end loop;
phase_flag :='0';
phase_flag1 :='0';
phase1 :="00";
cnt :=0;
elsif symbol_clk'event and symbol_clk='1' then
wr_cnt <=wr_cnt+1;
if wr_cnt>238 then --239
rd_ena:='1';
end if;
if rd_ena='1' then
rd_cnt <=rd_cnt+1;
end if;
ram_in<=frame_reg1(13);
frame_reg1(1 to 13) <=frame_reg1(0 to 12);
frame_reg1(0) <=data_in_i & data_in_q;
frame_reg2(1 to 13) <=frame_reg2(0 to 12);
frame_reg2(0) <=ram_out;
for i in 0 to 10 loop
if bakema(i)='0' then
tmp1_i(i):=frame_reg1(3+i)(9 downto 5);
tmp1_q(i):=frame_reg1(3+i)(4 downto 0);
tmp2_i(i):=frame_reg2(3+i)(9 downto 5);
tmp2_q(i):=frame_reg2(3+i)(4 downto 0);
else
tmp1_i(i):=not frame_reg1(3+i)(9 downto 5);
tmp1_q(i):=not frame_reg1(3+i)(4 downto 0);
tmp2_i(i):=not frame_reg2(3+i)(9 downto 5);
tmp2_q(i):=not frame_reg2(3+i)(4 downto 0);
end if;
end loop;
sum1_i:=conv_std_logic_vector(0,9)+tmp1_i(0)+tmp1_i(1)+tmp1_i(2)+tmp1_i(3)+tmp1_i(4)+tmp1_i(5)+tmp1_i(6)+tmp1_i(7)+tmp1_i(8)+tmp1_i(9)+tmp1_i(10);
sum2_i:=conv_std_logic_vector(0,9)+tmp2_i(0)+tmp2_i(1)+tmp2_i(2)+tmp2_i(3)+tmp2_i(4)+tmp2_i(5)+tmp2_i(6)+tmp2_i(7)+tmp2_i(8)+tmp2_i(9)+tmp2_i(10);
sum1_q:=conv_std_logic_vector(0,9)+tmp1_q(0)+tmp1_q(1)+tmp1_q(2)+tmp1_q(3)+tmp1_q(4)+tmp1_q(5)+tmp1_q(6)+tmp1_q(7)+tmp1_q(8)+tmp1_q(9)+tmp1_q(10);
sum2_q:=conv_std_logic_vector(0,9)+tmp2_q(0)+tmp2_q(1)+tmp2_q(2)+tmp2_q(3)+tmp2_q(4)+tmp2_q(5)+tmp2_q(6)+tmp2_q(7)+tmp2_q(8)+tmp2_q(9)+tmp2_q(10);
if abs(sum1_i)>conv_std_logic_vector(th1,9) and abs(sum2_i)>conv_std_logic_vector(th1,9) and
abs(sum1_q)>conv_std_logic_vector(th1,9) and abs(sum2_q)>conv_std_logic_vector(th1,9) then
frame_find:='1';
end if;
frame_syn<=frame_find;
if frame_find='1' then
if count1<255 then
count1:=count1+1;
else
count1:=0;
end if;
if count1=1 then --失步判决
--temp1_i<=abs(sum1_i);
--temp2_i<=abs(sum2_i);
--temp1_q<=abs(sum1_q);
--temp2_q<=abs(sum2_q);
if abs(sum1_i)<conv_std_logic_vector(th2,9) or abs(sum2_i)<conv_std_logic_vector(th2,9) or
abs(sum1_q)<conv_std_logic_vector(th2,9) or abs(sum2_q)<conv_std_logic_vector(th2,9) then
asyn_cnt1:=asyn_cnt1+1;
end if;
if asyn_cnt2<19 then
asyn_cnt2:=asyn_cnt2+1;
else
asyn_cnt2:=0;
asyn_cnt1:=0;
end if;
if asyn_cnt1=10 then
wr_cnt <=0;
rd_cnt <=0;
asyn_cnt1 :=0;
asyn_cnt2 :=0;
frame_find :='0';
phase1 :="00";
count1 :=0;
frame_pulse <='0';
frame_syn <='0';
rd_ena :='0';
phase_flag :='0';
phase_flag1 :='0';
phase1 :="00";
cnt :=0;
for i in 0 to 13 loop
frame_reg1(i)<=conv_std_logic_vector(0,10);
frame_reg2(i)<=conv_std_logic_vector(0,10);
end loop;
end if;
end if;
if count1=1 then --产生译码帧使能
frame_pulse<='0';
if abs(sum1_i)>conv_std_logic_vector(th1,9) and abs(sum2_i)>conv_std_logic_vector(th1,9) and
abs(sum1_q)>conv_std_logic_vector(th1,9) and abs(sum2_q)>conv_std_logic_vector(th1,9) then
if sum2_i(8)='0' and sum2_q(8)='0' then
phase(cnt):="00";
elsif sum2_i(8)='1' and sum2_q(8)='0' then
phase(cnt):="01";
elsif sum2_i(8)='0' and sum2_q(8)='1' then
phase(cnt):="10";
else
phase(cnt):="11";
end if;
cnt:=cnt+1;
end if;
if cnt=1 then --首次送出
if phase_flag='0' then
phase1:=phase(0);
phase_flag:='1';
end if;
elsif cnt=6 then --校验送出
cnt:=0;
if phase(0)=phase(1) and phase(1)=phase(2)
and phase(2)=phase(3)and phase(3)=phase(4) and phase(4)=phase(5) then
if phase_flag1='0' then
--phase_flag1:='1';
phase1:=phase(0);
end if;
end if;
end if;
else
frame_pulse<='1';
end if;
if count1=1 then
if phase1="00" then
tmp_sum:=conv_std_logic_vector(0,8)+frame_reg2(0)(9 downto 5)+frame_reg2(1)(9 downto 5)+frame_reg2(2)(9 downto 5)
+frame_reg2(0)(4 downto 0)+frame_reg2(1)(4 downto 0)+frame_reg2(2)(4 downto 0);
elsif phase1="01" then
tmp_sum:=conv_std_logic_vector(0,8)-frame_reg2(0)(9 downto 5)-frame_reg2(1)(9 downto 5)-frame_reg2(2)(9 downto 5)
+frame_reg2(0)(4 downto 0)+frame_reg2(1)(4 downto 0)+frame_reg2(2)(4 downto 0);
elsif phase1="10" then
tmp_sum:=conv_std_logic_vector(0,8)+frame_reg2(0)(9 downto 5)+frame_reg2(1)(9 downto 5)+frame_reg2(2)(9 downto 5)
-frame_reg2(0)(4 downto 0)-frame_reg2(1)(4 downto 0)-frame_reg2(2)(4 downto 0);
elsif phase1="11" then
tmp_sum:=conv_std_logic_vector(0,8)-frame_reg2(0)(9 downto 5)-frame_reg2(1)(9 downto 5)-frame_reg2(2)(9 downto 5)
-frame_reg2(0)(4 downto 0)-frame_reg2(1)(4 downto 0)-frame_reg2(2)(4 downto 0);
end if;
symbol_out<=tmp_sum(7);
end if;
if phase1="00" then
tmp_data_out_i<=frame_reg2(13)(9 downto 5);
tmp_data_out_q<=frame_reg2(13)(4 downto 0);
elsif phase1="01" then
tmp_data_out_i<=frame_reg2(13)(4 downto 0);
tmp_data_out_q<=not frame_reg2(13)(9 downto 5);
elsif phase1="10" then
tmp_data_out_i<=not frame_reg2(13)(4 downto 0);
tmp_data_out_q<=frame_reg2(13)(9 downto 5);
else
tmp_data_out_i<=not frame_reg2(13)(9 downto 5);
tmp_data_out_q<=not frame_reg2(13)(4 downto 0);
end if;
--if tmp_data_out_i(4)='1' then
-- data_out_i<=tmp_data_out_i+'1';
--else
data_out_i<=tmp_data_out_i;
--end if;
--if tmp_data_out_q(4)='1' then
-- data_out_q<=tmp_data_out_q+'1';
--else
data_out_q<=tmp_data_out_q;
--end if;
--if tmp_data_out_q="10000" then
-- data_out_q<="10001";
--else
-- data_out_q<=tmp_data_out_q;
--end if;
end if;
end if;
end process;
------------用于仿真的测试数据------------------------
--process(symbol_clk,reset)
--variable cntx :integer range 0 to 255;
--variable cnty :integer range 0 to 2047;
--variable cnt :integer range 0 to 2047;
--begin
-- if reset='0' then
-- cntx:=0;
-- cnty:=0;
-- cnt:=0;
-- data_in_i<="00000";
-- data_in_q<="00000";
-- elsif symbol_clk 'event and symbol_clk='1' then
--if cnt<520 then
-- cnt:=cnt+1;
-- if cntx<=12 then
-- data_in_i<=bakema(12-cntx) & not (bakema(12-cntx)) & not (bakema(12-cntx)) & not (bakema(12-cntx)) & not (bakema(12-cntx));
-- data_in_q<=bakema(12-cntx) & not (bakema(12-cntx)) & not (bakema(12-cntx)) & not (bakema(12-cntx)) & not (bakema(12-cntx));
-- else
-- data_in_i<=conv_std_logic_vector(cntx,5);
-- data_in_q<=conv_std_logic_vector(cntx+cnty,5);
-- end if;
-- if cntx<255 then
-- cntx:=cntx+1;
-- else
-- cntx:=0;
-- end if;
-- if cnty<2047 then
-- cnty:=cnty+1;
-- else
-- cnty:=0;
-- end if;
--else
-- data_in_i<=conv_std_logic_vector(0,5);
-- data_in_q<=conv_std_logic_vector(0,5);
--END IF;
-- end if;
--end process;
----------------------------------------------------
end bh;⌨️ 快捷键说明
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