shift20.vhd

完整的TPC编译码VHDL程序

LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

ENTITY shift20 IS
	PORT
	(
		clk		                       : in   std_logic;
	 di                          : in   std_logic_vector(15 downto 0);
  do                          : out  std_logic_vector(15 downto 0)
	);
END entity;
ARCHITECTURE rtl OF shift20 IS
signal shf0,shf1,shf2,shf3,shf4,shf5,shf6,shf7,shf8,shf9  : std_logic_vector(15 downto 0);
signal shf10,shf11,shf12,shf13,shf14,shf15,shf16,shf17,shf18,shf19  : std_logic_vector(15 downto 0);


begin
 process(clk)
 begin
   if clk'event and clk='1' then
    shf0<=di;
    shf1<=shf0;
    shf2<=shf1;
    shf3<=shf2;
    shf4<=shf3;
    shf5<=shf4;
    shf6<=shf5;
    shf7<=shf6;
    shf8<=shf7;
    shf9<=shf8;
    shf10<=shf9;
    shf11<=shf10;
    shf12<=shf11;
    shf13<=shf12;
    shf14<=shf13;
    shf15<=shf14;
    shf16<=shf15;
    shf17<=shf16;
    shf18<=shf17;
    shf19<=shf18;
    do<=shf9;
   end if;
 end process;

end rtl;