outbuf.vhd

完整的TPC编译码VHDL程序

LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

ENTITY outbuf IS
	PORT
	(inclk		                   : in  std_logic;
  outclk                    : in  std_logic;
  turn                      : in  std_logic;
  wcol                      : in  std_logic_vector(2 downto 0);
  wrow                      : in  std_logic_vector(5 downto 0);
  we                        : in  std_logic;
  lu0,lu1,lu2,lu3           : in  std_logic;--_vector(4 downto 0);
  iteration_num             : in  std_logic_vector(3 downto 0);
  save_ena                  : in  std_logic; 
                   
  tcnt0                     : out std_logic_vector(4 downto 0);
  tcnt1                     : out std_logic_vector(4 downto 0);
  tre                       : out std_logic;
  tre2                      : out std_logic;
  owe0,owe1                 : out std_logic;
  out_col                   : out std_logic_vector(2 downto 0);
  out_row                   : out std_logic_vector(5 downto 0);
  --olu0,olu1,olu2,olu3       : out std_logic_vector(4 downto 0);
  --olu                       : out std_logic_vector(3 downto 0);
  tramq0,tramq1             : out std_logic;
  toutq                       : out std_logic
	);
END entity;
ARCHITECTURE rtl OF outbuf  IS
signal  cnt0,cnt0_temp0,cnt0_temp1                : std_logic_vector(4 downto 0);
signal  cnt1,cnt1_temp                            : std_logic_vector(4 downto 0);
signal  re,retemp0,retemp1,retemp2,retemp3        : std_logic;

signal we0,we1         : std_logic;
signal  col_temp0      : std_logic_vector(2 downto 0);
signal  row_temp0      : std_logic_vector(5 downto 0);
signal  lu             : std_logic_vector(3 downto 0);
signal lu0_temp,lu1_temp,lu2_temp,lu3_temp    : std_logic_vector(4 downto 0);
--==============================================
signal ramq0,ramq1           : std_logic_vector(0 downto 0);
signal outq,outq_temp                  : std_logic;
signal save,save_temp                  : std_logic;
              
component outram IS
	PORT
	(
		data		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
		wren		: IN STD_LOGIC  := '1';
		wraddress		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		rdaddress		: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
		rden		: IN STD_LOGIC  := '1';
		wrclock		: IN STD_LOGIC ;
		rdclock		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
	);
END component;

component op_ena_shift IS
   PORT(clk              : in std_logic;
        input           : in std_logic;
        output          : out std_logic
	   );
END  component;



begin

process(outclk)
begin
   if outclk'event and outclk='1' then
       if turn='1' then
          cnt0<="00010";
       else
          case cnt0 is
              when "10001"=>cnt0<="00010";
              when others=>cnt0<=cnt0+"00001";
          end case;
       end if;
      cnt0_temp0<=cnt0;
      cnt0_temp1<=cnt0_temp0;
      tcnt0<=cnt0_temp0;
   end if;
end process;

process(outclk)
begin
   if outclk'event and outclk='1' then
       if turn='1' then
          cnt1<="00010";
       else
          case cnt0 is
              when "10001"=>case cnt1 is
                                  when "10001"=>cnt1<="00010";
                                  when others=>cnt1<=cnt1+"00001";
                             end case;
              when others=>null;
          end case;
       end if;
      cnt1_temp<=cnt1; 
      tcnt1<=cnt1_temp;

   end if;
end process;

process(outclk)
begin
   if outclk'event and outclk='1' then
      case save_ena is
          when '1'=>save<=not save;
          when '0'=>null;
      end case;
   retemp0<=re;
   retemp1<=retemp0;
   retemp2<=retemp1;
   retemp3<=retemp2;
   tre<=retemp1;--re;
   tre2<=save;
   end if;
end process;

save_sft: op_ena_shift PORT map(outclk,save,re);

process(inclk)
begin
   if inclk'event and inclk='1' then
       save_temp<=save;
   end if;
end process;


--===============================================

process(inclk)
begin
   if inclk'event and inclk='1' then
      case iteration_num is
          when "1001"=>--we0<=we and not save;
                       --we1<=we and save;
                       we0<=we and save_temp;
                       we1<=we and not save_temp;
          when others=>we0<='0';
                       we1<='0';
      end case;
      col_temp0<=wcol;
      row_temp0<=wrow;
      lu<=lu3 & lu2 & lu1 & lu0;
      --lu0_temp<=lu0;
      --lu1_temp<=lu1;
      --lu2_temp<=lu2;
      --lu3_temp<=lu3;


      out_col<=col_temp0;
      out_row<=row_temp0;
      owe0<=we0;
      owe1<=we1;
      --olu0<=lu0_temp;
      --olu1<=lu1_temp;
      --olu2<=lu2_temp;
      --olu3<=lu3_temp; 
      --olu<=lu;
   end if;
end process;

--=================================
outram_inst0 : outram PORT MAP (
		lu,
		we0,
		row_temp0(4 downto 0) & col_temp0,
		cnt0_temp0 & cnt1_temp,
		re,
		inclk,
		outclk,
		ramq0
	);
outram_inst1 : outram PORT MAP (
		lu,
		we1,
		row_temp0(4 downto 0) & col_temp0,
		cnt0_temp0 & cnt1_temp,
		not re,
		inclk,
		outclk,
		ramq1
	);

process(outclk)
begin
   if outclk'event and outclk='1' then
      tramq0<=ramq0(0);
      tramq1<=ramq1(0);
   end if;
end process;

process(outclk)
begin
   if outclk'event and outclk='1' then
      case retemp1 is
          when '1'=>outq<=ramq0(0);
          when '0'=>outq<=ramq1(0);
      end case;
      toutq<=outq;
   end if;
end process;




end rtl;