lu.vhd

完整的TPC编译码VHDL程序

LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

ENTITY lu IS
	PORT
	(
  clk		                         : in  std_logic;
  maxbit                             : in  std_logic;
  mw,mow,mzw                         : in  std_logic_vector(9 downto 0);
  mv,mov,mzv                         : in  std_logic;
  --beta                               : in  std_logic_vector(8 downto 0);
  dem                                : in  std_logic_vector(4 downto 0);
  romadd                             : in  std_logic_vector(3 downto 0);

  du                                 : out std_logic_vector(9 downto 0);
  de                                 : out std_logic_vector(9 downto 0)
  --t_lu_adda                          : out std_logic_vector(8 downto 0); 
  --t_lu_addb                          : out std_logic_vector(8 downto 0);
  --t_lu_temp                          : out std_logic_vector(8 downto 0);
  --t_lu_flag                          : out std_logic_vector(2 downto 0);
  --t_mw                               : out std_logic_vector(8 downto 0);
  --t_mo                               : out std_logic_vector(8 downto 0);
  --t_mz                               : out std_logic_vector(8 downto 0)

	);
END entity;

ARCHITECTURE rtl OF lu IS
signal lu_flag,lu_flag_temp0,lu_flag_temp1                 : std_logic_vector(2 downto 0);
signal lu_adda,lu_addb         : std_logic_vector(9 downto 0);
signal le_adda,le_addb         : std_logic_vector(9 downto 0);
signal lu,le                   : std_logic_vector(9 downto 0);
signal lutemp,lutemp1          : std_logic_vector(9 downto 0);
signal demtemp                 : std_logic_vector(9 downto 0);
signal demtemp0,demtemp1,demtemp2       : std_logic_vector(9 downto 0);

signal mwt,mowt,mzwt           : std_logic_vector(9 downto 0);
signal mwt0,mowt0,mzwt0        : std_logic_vector(9 downto 0);
signal mvt,movt,mzvt           : std_logic;
signal beta,betatemp                    : std_logic_vector(9 downto 0);
--constant beta                  : std_logic_vector(9 downto 0):="0000001111";
component luadd IS
	PORT
	(
		dataa		: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
		datab		: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
		result		: OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
	);
END component;

component betarom is
PORT
	(
		address		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
		clock		: IN STD_LOGIC ;
		q		    : OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
	);

end component;
          
begin

betadata: betarom port map (romadd,clk,beta);

--process(clk)
--begin
--if clk'event and clk='1' then
--   beta<=betatemp;
--end if;
--end process;


-- there is one clock delay of maxbit to mw .
process(clk)
begin
   if clk'event and clk='1' then
     case mw(9) is
         when '0'=>case mw(0) is
                       when '1'=>mwt0<=mw(9) & mw(9 downto 1)+'1';
                       when '0'=>mwt0<=mw(9) & mw(9 downto 1);
                    end case;
         when '1'=>mwt0<=mw(9) & mw(9 downto 1);
     end case;
     case mow(9) is
         when '0'=>case mow(0) is
                       when '1'=>mowt0<=mow(9) & mow(9 downto 1)+'1';
                       when '0'=>mowt0<=mow(9) & mow(9 downto 1);
                    end case;
         when '1'=>mowt0<=mow(9) & mow(9 downto 1);
     end case;
     case mzw(9) is
         when '0'=>case mzw(0) is
                       when '1'=>mzwt0<=mzw(9) & mzw(9 downto 1)+'1';
                       when '0'=>mzwt0<=mzw(9) & mzw(9 downto 1);
                    end case;
         when '1'=>mzwt0<=mzw(9) & mzw(9 downto 1);
     end case;

     -- mwt0<=mw(9 downto 1);
     -- mowt0<=mow(9 downto 1);
     -- mzwt0<=mzw(9 downto 1);

      mwt<=mwt0;
      mowt<=mowt0;
      mzwt<=mzwt0;

      mvt<=mv;
      movt<=mov;
      mzvt<=mzv;

      demtemp0<=dem(4) & dem(4) & dem(4) & dem(4) & dem(4) & dem;
      demtemp1<=demtemp0;
      demtemp2<=demtemp1;
      demtemp<=demtemp2;

      lu_flag<=maxbit & movt & mzvt;


   end if;
end process;



process(clk)
begin
if clk'event and clk='1' then

 case lu_flag is
    when "111"=>lu_adda<=mzwt;
                lu_addb<=mwt;
    when "110"=>lu_adda<="0000000000";
                lu_addb<=beta;
    when "011"=>lu_adda<=mwt;
                lu_addb<=mowt;
    when "001"=>lu_adda<=beta;
                lu_addb<="0000000000";
    when others=>null; 
 end case;
end if;
end process;



lu_adder: luadd port map(lu_adda,lu_addb,lu);
process(clk)
begin
   if clk'event and clk='1' then
      lu_flag_temp0<=lu_flag;
      lu_flag_temp1<=lu_flag_temp0;
      lutemp<=lu;
      lutemp1<=lutemp;
   end if;
end process;

process(clk)
begin
if clk'event and clk='1' then
   case lu_flag_temp1 is
      when "111"=>le_adda<=lutemp;
                  le_addb<=demtemp;
      when "110"=>le_adda<=lutemp;
                  le_addb<="0000000000";
      when "011"=>le_adda<=lutemp;
                  le_addb<=demtemp;
      when "001"=>le_adda<=lutemp;
                  le_addb<="0000000000";
      when others=>null; 
  end case;
end if;
end process;


le_adder: luadd port map(le_adda,le_addb,le);

process(clk)
begin
  if clk'event and clk='1' then
     du<=lutemp1;
     de<=le;
  end if;
end process;

end rtl;