core32.vhd

完整的TPC编译码VHDL程序

  errp0,errp1,errp2,errp3,errp4,errp5,
  errp6,errp7,errp8,errp9,errpa,errpb,
  errpc,errpd,errpe,errpf,

  ptemp0,ptemp1,ptemp2,ptemp3,
  ptemp4,ptemp5,ptemp6,ptemp7,
  ptemp8,ptemp9,ptempa,ptempb,
  ptempc,ptempd,ptempe,ptempf,

  csq0,csq1,csq2,csq3,csq4,csq5,
  csq6,csq7,csq8,csq9,csqa,csqb,
  csqc,csqd,csqe,csqf 

	);




shift_mid_inst: shift_mid	PORT map(clk,mid_data,mid_temp1);

process(clk)
begin
  if clk'event and clk='1' then
    wd3<=mid_temp1(19) & mid_temp1(19 downto 15);
    wd2<=mid_temp1(14) & mid_temp1(14 downto 10);
    wd1<=mid_temp1(9)  & mid_temp1(9 downto 5);
    wd0<=mid_temp1(4)  & mid_temp1(4 downto 0);

    --pri_temp0<=pri;
    --pri_temp1<=pri_temp0;
    --pri_temp2<=pri_temp1;
    --twd3<=mid_temp2(19 downto 15);
    --twd2<=mid_temp2(14 downto 10);
    --twd1<=mid_temp2(9 downto 5);
    --twd0<=mid_temp2(4 downto 0);
    --tpr3<=pri(19 downto 15);
    --tpr2<=pri(14 downto 10);
    --tpr1<=pri(9 downto 5);
    --tpr0<=pri(4 downto 0);
    --twd3<=wd3;
    --twd2<=wd2;
    --twd1<=wd1;
    --twd0<=wd0;


     --wt0<=w0;
     --wt1<=w1;
     --wt2<=w2;
     --wt3<=w3;
     --wt4<=w4;
     --wt5<=w5;
     --wt6<=w6;
     --wt7<=w7;
     --wt8<=w8;
     --wt9<=w9;
     --wta<=wa;
     --wtb<=wb;
     --wtc<=wc;
     --wtd<=wd;
     --wte<=we;
     --wtf<=wf;


     --tseqv<=seqv;

  end if;
end process;

w_inst0: weight port map (clk,rbegin_temp29,wd0,wd1,wd2,wd3,csq0,w0);
w_inst1: weight port map (clk,rbegin_temp29,wd0,wd1,wd2,wd3,csq1,w1);
w_inst2: weight port map (clk,rbegin_temp29,wd0,wd1,wd2,wd3,csq2,w2);
w_inst3: weight port map (clk,rbegin_temp29,wd0,wd1,wd2,wd3,csq3,w3);
w_inst4: weight port map (clk,rbegin_temp29,wd0,wd1,wd2,wd3,csq4,w4);
w_inst5: weight port map (clk,rbegin_temp29,wd0,wd1,wd2,wd3,csq5,w5);
w_inst6: weight port map (clk,rbegin_temp29,wd0,wd1,wd2,wd3,csq6,w6);
w_inst7: weight port map (clk,rbegin_temp29,wd0,wd1,wd2,wd3,csq7,w7);
w_inst8: weight port map (clk,rbegin_temp29,wd0,wd1,wd2,wd3,csq8,w8);
w_inst9: weight port map (clk,rbegin_temp29,wd0,wd1,wd2,wd3,csq9,w9);
w_insta: weight port map (clk,rbegin_temp29,wd0,wd1,wd2,wd3,csqa,wa);
w_instb: weight port map (clk,rbegin_temp29,wd0,wd1,wd2,wd3,csqb,wb);
w_instc: weight port map (clk,rbegin_temp29,wd0,wd1,wd2,wd3,csqc,wc);
w_instd: weight port map (clk,rbegin_temp29,wd0,wd1,wd2,wd3,csqd,wd);
w_inste: weight port map (clk,rbegin_temp29,wd0,wd1,wd2,wd3,csqe,we);
w_instf: weight port map (clk,rbegin_temp29,wd0,wd1,wd2,wd3,csqf,wf);



validflag<=errpf(6) & errpe(6) & errpd(6) & errpc(6) & errpb(6) & errpa(6) & errp9(6) & errp8(6) & 
           errp7(6) & errp6(6) & errp5(6) & errp4(6) & errp3(6) & errp2(6) & errp1(6) & errp0(6); 

shift20_inst: shift20 port map (clk,validflag,seqv);



shift18_inst0: shift18	PORT map(clk,csq0,wsq0);
shift18_inst1: shift18	PORT map(clk,csq1,wsq1);
shift18_inst2: shift18	PORT map(clk,csq2,wsq2);
shift18_inst3: shift18	PORT map(clk,csq3,wsq3);
shift18_inst4: shift18	PORT map(clk,csq4,wsq4);
shift18_inst5: shift18	PORT map(clk,csq5,wsq5);
shift18_inst6: shift18	PORT map(clk,csq6,wsq6);
shift18_inst7: shift18	PORT map(clk,csq7,wsq7);
shift18_inst8: shift18	PORT map(clk,csq8,wsq8);
shift18_inst9: shift18	PORT map(clk,csq9,wsq9);
shift18_insta: shift18	PORT map(clk,csqa,wsqa);
shift18_instb: shift18	PORT map(clk,csqb,wsqb);
shift18_instc: shift18	PORT map(clk,csqc,wsqc);
shift18_instd: shift18	PORT map(clk,csqd,wsqd);
shift18_inste: shift18	PORT map(clk,csqe,wsqe);
shift18_instf: shift18	PORT map(clk,csqf,wsqf);

max0: max 
	PORT map
	(
  clk,
  wsq0(0),wsq1(0),wsq2(0),wsq3(0),wsq4(0),
  wsq5(0),wsq6(0),wsq7(0),wsq8(0),wsq9(0),
  wsqa(0),wsqb(0),wsqc(0),wsqd(0),wsqe(0),wsqf(0),
  w0,w1,w2,w3,w4,w5,w6,w7,w8,w9, wa,wb,wc,wd,we,wf,
  seqv,
  maxw0,maxnum0,maxv0,
  maxonew0,maxonenum0,maxonev0,
  maxzerow0,maxzeronum0,maxzerov0
	);
max1: max 
	PORT map
	(
  clk,
  wsq0(1),wsq1(1),wsq2(1),wsq3(1),wsq4(1),
  wsq5(1),wsq6(1),wsq7(1),wsq8(1),wsq9(1),
  wsqa(1),wsqb(1),wsqc(1),wsqd(1),wsqe(1),wsqf(1),
  w0,w1,w2,w3,w4,w5,w6,w7,w8,w9, wa,wb,wc,wd,we,wf,
  seqv,
  maxw1,maxnum1,maxv1,
  maxonew1,maxonenum1,maxonev1,
  maxzerow1,maxzeronum1,maxzerov1
	);

max2: max 
	PORT map
	(
  clk,
  wsq0(2),wsq1(2),wsq2(2),wsq3(2),wsq4(2),
  wsq5(2),wsq6(2),wsq7(2),wsq8(2),wsq9(2),
  wsqa(2),wsqb(2),wsqc(2),wsqd(2),wsqe(2),wsqf(2),
  w0,w1,w2,w3,w4,w5,w6,w7,w8,w9, wa,wb,wc,wd,we,wf,
  seqv,
  maxw2,maxnum2,maxv2,
  maxonew2,maxonenum2,maxonev2,
  maxzerow2,maxzeronum2,maxzerov2
	);
max3: max 
	PORT map
	(
  clk,
  wsq0(3),wsq1(3),wsq2(3),wsq3(3),wsq4(3),
  wsq5(3),wsq6(3),wsq7(3),wsq8(3),wsq9(3),
  wsqa(3),wsqb(3),wsqc(3),wsqd(3),wsqe(3),wsqf(3),
  w0,w1,w2,w3,w4,w5,w6,w7,w8,w9, wa,wb,wc,wd,we,wf,
  seqv,
  maxw3,maxnum3,maxv3,
  maxonew3,maxonenum3,maxonev3,
  maxzerow3,maxzeronum3,maxzerov3
	);


--process(clk)
--begin
--   if clk'event and clk='1' then
       --tmaxw0<=maxw0;
       --tmaxnum0<=maxnum0;
       --tmaxv0<=maxv0;
       --tmaxonew0<=maxonew0;
       --tmaxonenum0<=maxonenum0;
       --tmaxonev0<=maxonev0;
       --tmaxzerow0<=maxzerow0;
       --tmaxzeronum0<=maxzeronum0;
       --tmaxzerov0<=maxzerov0;

       --tmaxw1<=maxw1;
       --tmaxnum1<=maxnum1;
       --tmaxv1<=maxv1;
       --tmaxonew1<=maxonew1;
       --tmaxonenum1<=maxonenum1;
       --tmaxonev1<=maxonev1;
       --tmaxzerow1<=maxzerow1;
       --tmaxzeronum1<=maxzeronum1;
       --tmaxzerov1<=maxzerov1;

       --tmaxw2<=maxw2;
       --tmaxnum2<=maxnum2;
       --tmaxv2<=maxv2;
       --tmaxonew2<=maxonew2;
       --tmaxonenum2<=maxonenum2;
       --tmaxonev2<=maxonev2;
       --tmaxzerow2<=maxzerow2;
       --tmaxzeronum2<=maxzeronum2;
       --tmaxzerov2<=maxzerov2;

       --tmaxw3<=maxw3;
       --tmaxnum3<=maxnum3;
       --tmaxv3<=maxv3;
       --tmaxonew3<=maxonew3;
       --tmaxonenum3<=maxonenum3;
       --tmaxonev3<=maxonev3;
       --tmaxzerow3<=maxzerow3;
       --tmaxzeronum3<=maxzeronum3;
       --tmaxzerov3<=maxzerov3;

--   end if;
--end process;

sqshift6_inst0: sqshift6 PORT map(clk,wsq0,lsq0);
sqshift6_inst1: sqshift6 PORT map(clk,wsq1,lsq1);
sqshift6_inst2: sqshift6 PORT map(clk,wsq2,lsq2);
sqshift6_inst3: sqshift6 PORT map(clk,wsq3,lsq3);
sqshift6_inst4: sqshift6 PORT map(clk,wsq4,lsq4);
sqshift6_inst5: sqshift6 PORT map(clk,wsq5,lsq5);
sqshift6_inst6: sqshift6 PORT map(clk,wsq6,lsq6);
sqshift6_inst7: sqshift6 PORT map(clk,wsq7,lsq7);
sqshift6_inst8: sqshift6 PORT map(clk,wsq8,lsq8);
sqshift6_inst9: sqshift6 PORT map(clk,wsq9,lsq9);
sqshift6_insta: sqshift6 PORT map(clk,wsqa,lsqa);
sqshift6_instb: sqshift6 PORT map(clk,wsqb,lsqb);
sqshift6_instc: sqshift6 PORT map(clk,wsqc,lsqc);
sqshift6_instd: sqshift6 PORT map(clk,wsqd,lsqd);
sqshift6_inste: sqshift6 PORT map(clk,wsqe,lsqe);
sqshift6_instf: sqshift6 PORT map(clk,wsqf,lsqf);


s16_1_inst : s16_1 PORT MAP (
		clock	 => clk,
		data15x	 => lsqf,
		data14x	 => lsqe,
		data13x	 => lsqd,
		data12x	 => lsqc,
		data11x	 => lsqb,
		data10x	 => lsqa,
		data9x	 => lsq9,
		data8x	 => lsq8,
		data7x	 => lsq7,
		data6x	 => lsq6,
		data5x	 => lsq5,
		data4x	 => lsq4,
		data3x	 => lsq3,
		data2x	 => lsq2,
		data1x	 => lsq1,
		data0x	 => lsq0,
		sel	 => maxnum0,
		result	 => maxbit
	);


shift_pri_inst: shift_pri	PORT map(clk,pri_data,pri);
shift_mid2_inst: shift_mid2	PORT map(clk,mid_temp1,mid_temp2);

lu_inst0: lu 
PORT MAP
(clk,maxbit(0),maxw0,maxonew0,maxzerow0,maxv0,maxonev0,maxzerov0,mid_temp2(4 downto 0),itenum,du0,de0);
lu_inst1: lu 
PORT MAP
(clk,maxbit(1),maxw1,maxonew1,maxzerow1,maxv1,maxonev1,maxzerov1,mid_temp2(9 downto 5),itenum,du1,de1);
lu_inst2: lu 
PORT MAP
(clk,maxbit(2),maxw2,maxonew2,maxzerow2,maxv2,maxonev2,maxzerov2,mid_temp2(14 downto 10),itenum,du2,de2);
lu_inst3: lu 
PORT MAP
(clk,maxbit(3),maxw3,maxonew3,maxzerow3,maxv3,maxonev3,maxzerov3,mid_temp2(19 downto 15),itenum,du3,de3);


process(clk)
begin
   if clk'event and clk='1' then
      tdu0<=du0(9);--pri(4) & pri(4) & pri(4) & pri(4) & pri(4 downto 0);--
      tde0<=de0;
      tdu1<=du1(9);--pri(9) & pri(9) & pri(9) & pri(9) & pri(9 downto 5);--
      tde1<=de1;
      tdu2<=du2(9);--pri(14) & pri(14) & pri(14) & pri(14) & pri(14 downto 10);--
      tde2<=de2;
      tdu3<=du3(9);--pri(19) & pri(19) & pri(19) & pri(19) & pri(19 downto 15);--
      tde3<=de3;
      tpri<=pri;
      --tp0<=pri(4 downto 0);
      --tp1<=pri(9 downto 5);
      --tp2<=pri(14 downto 10);
      --tp3<=pri(19 downto 15);
   end if;
end process;


process(clk)
begin
   if clk'event and clk='1' then
       if rst1='1' then
          col_ad0_temp0<="000";
       else
          case col_ad0_temp0 is
               when "101"=>col_ad0_temp0<="000";
               when others=>col_ad0_temp0<=col_ad0_temp0+"001";
          end case;
       end if;
       --t_set<=reset_sft;
       col_ad0_temp1<=col_ad0_temp0;
       t_colad<=col_ad0_temp1;
   end if;
end process;

reset_shift: shift_set 	PORT map	(clk,reset,reset_sft	);
process(clk)
begin
   if clk'event and clk='1' then
      rst0<=reset_sft;
      rst1<=rst0;
   end if;
end process;


process(clk)
begin
   if clk'event and clk='1' then
      if rst1='1' then
          row_ad<="111111";
      else
          case col_ad0_temp0 is
              when "000"=>row_ad<=row_ad+"000001";
              when others=>null;
          end case;
      end if;
    t_rowad<=row_ad;
   end if;
end process;


process(clk)
begin
  if clk'event and clk='1' then
     --case row_ad is
     --  when "000000"=>wetemp0<='1';
     --  when "011000"=>wetemp0<='0';
     --  when others=>null;
     --end case;
     case row_ad is
       when "000000"=>twe<='1';
       when "011000"=>twe<='0';
       when others=>null;
     end case;

  end if;
  --twe<=wetemp0;
end process;

--process(clk)
--begin
--  if clk'event and clk='1' then
--     iteration_t0<=itenum; 
--     iteration<=iteration_t0; 
--  end if;
--end process;



--outsft: outstr_shift PORT map(inclk,flag,outflag,saveflag);

end rtl;