core32.vhd

完整的TPC编译码VHDL程序

      --tda3<=da3;-----------------
      --tda2<=da2;-------------------
      --tda1<=da1;-------------------
      --tda0<=da0;-------------------



      hard(3)<=mid_data(19);
      hard(2)<=mid_data(14);
      hard(1)<=mid_data(9);
      hard(0)<=mid_data(4);

      hard_shf0<=hard;
      hard_shf1<=hard_shf0;
      hard_shf2<=hard_shf1;
      hard_shf3<=hard_shf2;
      hard_shf4<=hard_shf3;
      hard_shf5<=hard_shf4;
      hard_shf6<=hard_shf5;
      hard_shf7<=hard_shf6;

      hard_shf8<=hard_shf7;
      hard_shf9<=hard_shf8;
      hard_shf10<=hard_shf9;
      hard_shf11<=hard_shf10;
      hard_shf12<=hard_shf11;
      hard_shf13<=hard_shf12;
      hard_shf14<=hard_shf13;
      hard_shf15<=hard_shf14;
      hard_shf16<=hard_shf15;

      --hard_out<=hard_shf16;
      --hardo<=hard;
  end if;
end process;

inst0: abs_of_data 
   port map(
      clk,
      da0,da1,da2,da3,
      abs_d0,abs_d1,abs_d2,abs_d3
      );

process(clk)
begin
  if clk'event and clk='1' then
     fa0<=abs_d0;--(3 downto 0);
     fa1<=abs_d1;--(3 downto 0);
     fa2<=abs_d2;--(3 downto 0);
     fa3<=abs_d3;--(3 downto 0);
     --ab_d0<=fa0;--abs_d0(3 downto 0);
     --ab_d1<=fa1;--abs_d1(3 downto 0);
     --ab_d2<=fa2;--abs_d2(3 downto 0);
     --ab_d3<=fa3;--abs_d3(3 downto 0);
  end if;
end process;


findinst: find_small 
port map
(   clk,
    fa0,fa1,fa2,fa3,
    word_end_dly0,
    fmi0,fmi1,fmi2,fmi3,
    fminum0,fminum1,fminum2,fminum3
    );

--process(clk)
--begin
 -- if clk'event and clk='1' then
      --mi0<=fmi0;
      --mi1<=fmi1;
      --mi2<=fmi2;
      --mi3<=fmi3;

      --minum0<=fminum0;
      --minum1<=fminum1;
      --minum2<=fminum2;
      --minum3<=fminum3;
      
     --tm0<=m0;--
     --tm1<=m1;--
     --tm2<=m2;--
     --tm3<=m3;--

     --tmcol0<=mcol0;-- 
     --tmcol1<=mcol1; 
     --tmcol2<=mcol2; 
     --tmcol3<=mcol3;
 
     --tmnum0<=mnum0;
     --tmnum1<=mnum1;
     --tmnum2<=mnum2;
     --tmnum3<=mnum3;--



--  end if;
--end process;


sort4inst: sort4 
port map
(clk,
rbegin_temp3,
fmi0,fmi1,fmi2,fmi3,
shift_cnt0_temp4,
fminum0,fminum1,fminum2,fminum3,
m0,m1,m2,m3,mcol0,
mcol1,mcol2,mcol3,
mnum0,mnum1,mnum2,mnum3
);


process(clk)
begin
  if clk'event and clk='1' then
     if rbegin_temp7='1' then
        cnt1<="000";
     else
         case cnt1 is
            when "101"=>cnt1<="000";
            when others  =>cnt1<=cnt1+"1";
         end case;
     end if;

    --t_word_col<=word_col;
    --tcnt1<=cnt1;
  end if;
end process;

genseq: gen_tseq 
PORT map
( clk,		                              
  mcol0,mcol1,mcol2,mcol3,            
  mnum0,mnum1,mnum2,mnum3,            
  hard_shf16,                             
  cnt1,                               
  gseq0,gseq1,gseq2,gseq3,                
  gseq4,gseq5,gseq6,gseq7,                
  gseq8,gseq9,gseqa,gseqb,              
  gseqc,gseqd,gseqe,gseqf            
  );

--process(clk)
--begin
--  if clk'event and clk='1' then
--      tseq0<=gseq0;
--     tseq1<=gseq1;
--      tseq2<=gseq2;
--      tseq3<=gseq3;
--      tseq4<=gseq4;
--      tseq5<=gseq5;
--      tseq6<=gseq6;
--      tseq7<=gseq7;
--      tseq8<=gseq8;
--      tseq9<=gseq9;
--      tseqa<=gseqa;
--      tseqb<=gseqb;
--      tseqc<=gseqc;
--      tseqd<=gseqd;
--      tseqe<=gseqe;
--      tseqf<=gseqf;

      --tmaxbit<=maxbit;

--  end if;
--end process;


div_inst: div 
PORT MAP
( clk,	                                         
  rbegin_temp18,
  word_end_dly13,                                     
  gseq0,gseq1,gseq2,gseq3,gseq4,gseq5,             
  gseq6,gseq7,gseq8,gseq9,gseqa,                
  gseqb,gseqc,gseqd,gseqe,gseqf,            

  syn0,syn1,syn2,syn3,syn4,syn5,                 
  syn6,syn7,syn8,syn9,syna,                     
  synb,sync,synd,syne,synf,                 

  pari0,pari1,pari2,pari3,pari4,pari5,           
  pari6,pari7,pari8,pari9,paria,                
  parib,paric,parid,parie,parif        
  );

--process(clk)
--begin
--  if clk'event and clk='1' then
--   tsyn0<=syn0;
--   tsyn1<=syn1;
--   tsyn2<=syn2;
--   tsyn3<=syn3;
--   tsyn4<=syn4;
--   tsyn5<=syn5;
--   tsyn6<=syn6;
--   tsyn7<=syn7;
--   tsyn8<=syn8;
--   tsyn9<=syn9;
--   tsyna<=syna;
--   tsynb<=synb;
--   tsync<=sync;
--   tsynd<=synd;
--   tsyne<=syne;
--   tsynf<=synf;

--   tpari0<=pari0;
--   tpari1<=pari1;
--   tpari2<=pari2;
--   tpari3<=pari3;
--   tpari4<=pari4;
--   tpari5<=pari5;
--   tpari6<=pari6;
--   tpari7<=pari7;
--   tpari8<=pari8;
--   tpari9<=pari9;
--   tparia<=paria;
--   tparib<=parib;
--   tparic<=paric;
--   tparid<=parid;
--   tparie<=parie;
--   tparif<=parif;
--  end if;
--end process;

eptable0: eptable PORT map(syn0,clk,errp0);
eptable1: eptable PORT map(syn1,clk,errp1);
eptable2: eptable PORT map(syn2,clk,errp2);
eptable3: eptable PORT map(syn3,clk,errp3);
eptable4: eptable PORT map(syn4,clk,errp4);
eptable5: eptable PORT map(syn5,clk,errp5);
eptable6: eptable PORT map(syn6,clk,errp6);
eptable7: eptable PORT map(syn7,clk,errp7);
eptable8: eptable PORT map(syn8,clk,errp8);
eptable9: eptable PORT map(syn9,clk,errp9);
eptablea: eptable PORT map(syna,clk,errpa);
eptableb: eptable PORT map(synb,clk,errpb);
eptablec: eptable PORT map(sync,clk,errpc);
eptabled: eptable PORT map(synd,clk,errpd);
eptablee: eptable PORT map(synf,clk,errpf);



--process(clk)
--begin
--  if clk'event and clk='1' then
      --sv0<=errp0(6 downto 5);
      --sv1<=errp1(6 downto 5);
      --sv2<=errp2(6 downto 5);
      --sv3<=errp3(6 downto 5);
      --sv4<=errp4(6 downto 5);
      --sv5<=errp5(6 downto 5);
      --sv6<=errp6(6 downto 5);
      --sv7<=errp7(6 downto 5);
      --sv8<=errp8(6 downto 5);
      --sv9<=errp9(6 downto 5);
      --sva<=errpa(6 downto 5);
      --svb<=errpb(6 downto 5);
      --svc<=errpc(6 downto 5);
      --svd<=errpd(6 downto 5);
      --sve<=errpe(6 downto 5);
      --svf<=errpf(6 downto 5);

      --err_loc0<=errp0(4 downto 0);
      --err_loc1<=errp1(4 downto 0);
      --err_loc2<=errp2(4 downto 0);
      --err_loc3<=errp3(4 downto 0);
      --err_loc4<=errp4(4 downto 0);
      --err_loc5<=errp5(4 downto 0);
      --err_loc6<=errp6(4 downto 0);
      --err_loc7<=errp7(4 downto 0);
      --err_loc8<=errp8(4 downto 0);
      --err_loc9<=errp9(4 downto 0);
      --err_loca<=errpa(4 downto 0);
      --err_locb<=errpb(4 downto 0);
      --err_locc<=errpc(4 downto 0);
      --err_locd<=errpd(4 downto 0);
      --err_loce<=errpe(4 downto 0);
      --err_locf<=errpf(4 downto 0);

--  end if;
--end process;


sqshift_inst0: shiftseq	PORT map(clk,gseq0,cor_sq0);
sqshift_inst1: shiftseq	PORT map(clk,gseq1,cor_sq1);
sqshift_inst2: shiftseq	PORT map(clk,gseq2,cor_sq2);
sqshift_inst3: shiftseq	PORT map(clk,gseq3,cor_sq3);
sqshift_inst4: shiftseq	PORT map(clk,gseq4,cor_sq4);
sqshift_inst5: shiftseq	PORT map(clk,gseq5,cor_sq5);
sqshift_inst6: shiftseq	PORT map(clk,gseq6,cor_sq6);
sqshift_inst7: shiftseq	PORT map(clk,gseq7,cor_sq7);
sqshift_inst8: shiftseq	PORT map(clk,gseq8,cor_sq8);
sqshift_inst9: shiftseq	PORT map(clk,gseq9,cor_sq9);
sqshift_insta: shiftseq	PORT map(clk,gseqa,cor_sqa);
sqshift_instb: shiftseq	PORT map(clk,gseqb,cor_sqb);
sqshift_instc: shiftseq	PORT map(clk,gseqc,cor_sqc);
sqshift_instd: shiftseq	PORT map(clk,gseqd,cor_sqd);
sqshift_inste: shiftseq	PORT map(clk,gseqe,cor_sqe);
sqshift_instf: shiftseq	PORT map(clk,gseqf,cor_sqf);



--process(clk)
--begin
--  if clk'event and clk='1' then

--      tcsq0<=cor_sq0;
--      tcsq1<=cor_sq1;
--      tcsq2<=cor_sq2;
--      tcsq3<=cor_sq3;
--      tcsq4<=cor_sq4;
--      tcsq5<=cor_sq5;
--      tcsq6<=cor_sq6;
--      tcsq7<=cor_sq7;
--      tcsq8<=cor_sq8;
--      tcsq9<=cor_sq9;
--      tcsqa<=cor_sqa;
--      tcsqb<=cor_sqb;
--      tcsqc<=cor_sqc;
--      tcsqd<=cor_sqd;
--      tcsqe<=cor_sqe;
--      tcsqf<=cor_sqf;

--  end if;
--end process;
cnt1shift: shiftcnt1 PORT map(clk,cnt1,word_col);

process(clk)
begin
  if clk'event and clk='1' then
   ptemp0<=pari0;
   ptemp1<=pari1;
   ptemp2<=pari2;
   ptemp3<=pari3;
   ptemp4<=pari4;
   ptemp5<=pari5;
   ptemp6<=pari6;
   ptemp7<=pari7;
   ptemp8<=pari8;
   ptemp9<=pari9;
   ptempa<=paria;
   ptempb<=parib;
   ptempc<=paric;
   ptempd<=parid;
   ptempe<=parie;
   ptempf<=parif;
  end if;
end process;



cor16inst: cor16 
PORT map
(
  clk,
  cor_sq0,cor_sq1,cor_sq2,cor_sq3,cor_sq4,cor_sq5,
  cor_sq6,cor_sq7,cor_sq8,cor_sq9,cor_sqa,cor_sqb,
  cor_sqc,cor_sqd,cor_sqe,cor_sqf,

  word_col,