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outdata : out std_logic_vector(2 downto 0)
);
END component;
component cor16 IS
PORT
(
clk : in std_logic;
s0,s1,s2,s3,s4,s5 : in std_logic_vector(3 downto 0);
s6,s7,s8,s9,s10 : in std_logic_vector(3 downto 0);
s11,s12,s13,s14,s15 : in std_logic_vector(3 downto 0);
seq_col : in std_logic_vector(2 downto 0);
re0,re1,re2,re3,re4,re5 : in std_logic_vector(6 downto 0);
re6,re7,re8,re9,re10,re11 : in std_logic_vector(6 downto 0);
re12,re13,re14,re15 : in std_logic_vector(6 downto 0);
p0,p1,p2,p3,p4,p5,p6,p7 : in std_logic;
p8,p9,pa,pb,pc,pd,pe,pf : in std_logic;
cq0,cq1,cq2,cq3,cq4,cq5 : out std_logic_vector(3 downto 0);
cq6,cq7,cq8,cq9,cq10,cq11 : out std_logic_vector(3 downto 0);
cq12,cq13,cq14,cq15 : out std_logic_vector(3 downto 0)
);
END component;
component shift_mid IS
PORT
(
clk : in std_logic;
indata : in std_logic_vector(19 downto 0);
outdata : out std_logic_vector(19 downto 0)
);
END component;
component weight IS
PORT
(
clk : IN STD_LOGIC;
start : in std_logic;
a0,a1,a2,a3 : in std_logic_vector(5 downto 0);
s : in std_logic_vector(3 downto 0);
weight : out std_logic_vector(9 downto 0)
);
END component;
component shift18 IS
PORT
(
clk : in std_logic;
indata : in std_logic_vector(3 downto 0);
outdata : out std_logic_vector(3 downto 0)
);
END component;
component shift20 IS
PORT
(
clk : in std_logic;
di : in std_logic_vector(15 downto 0);
do : out std_logic_vector(15 downto 0)
);
END component;
component max IS
PORT
(
clk : in std_logic;
se0,se1,se2,se3,se4 : in std_logic;
se5,se6,se7,se8,se9 : in std_logic;
se10,se11,se12,se13,se14 : in std_logic;
se15 : in std_logic;
comw0,comw1,comw2,comw3,comw4 : in std_logic_vector(9 downto 0);
comw5,comw6,comw7,comw8,comw9 : in std_logic_vector(9 downto 0);
comw10,comw11,comw12,comw13,comw14 : in std_logic_vector(9 downto 0);
comw15 : in std_logic_vector(9 downto 0);
v : in std_logic_vector(15 downto 0);
maxw : out std_logic_vector(9 downto 0);
maxnum : out std_logic_vector(3 downto 0);
maxv : out std_logic;
maxonew : out std_logic_vector(9 downto 0);
maxonenum : out std_logic_vector(3 downto 0);
maxonev : out std_logic;
maxzerow : out std_logic_vector(9 downto 0);
maxzeronum : out std_logic_vector(3 downto 0);
maxzerov : out std_logic
);
END component;
component sqshift6 IS
PORT
(
clk : in std_logic;
indata : in std_logic_vector(3 downto 0);
outdata : out std_logic_vector(3 downto 0)
);
END component;
component s16_1 IS
PORT
(
clock : IN STD_LOGIC ;
data15x : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
data14x : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
data13x : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
data12x : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
data11x : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
data10x : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
data9x : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
data8x : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
data7x : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
data6x : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
data5x : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
data4x : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
data3x : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
data2x : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
data1x : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
data0x : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
sel : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END component;
component shift_mid2 IS
PORT
(
clk : in std_logic;
indata : in std_logic_vector(19 downto 0);
outdata : out std_logic_vector(19 downto 0)
);
END component;
component shift_pri IS
PORT
(
clk : in std_logic;
indata : in std_logic_vector(19 downto 0);
outdata : out std_logic_vector(19 downto 0)
);
END component;
component lu IS
PORT
(
clk : in std_logic;
maxbit : in std_logic;
mw,mow,mzw : in std_logic_vector(9 downto 0);
mv,mov,mzv : in std_logic;
dem : in std_logic_vector(4 downto 0);
romadd : in std_logic_vector(3 downto 0);
du : out std_logic_vector(9 downto 0);
de : out std_logic_vector(9 downto 0)
);
END component;
component shift_set IS
PORT
(
clk : in std_logic;
indata : in std_logic;
outdata : out std_logic
);
END component;
--component outstr_shift IS
-- PORT(clk : in std_logic;
-- input : in std_logic;
-- output : out std_logic;
-- output2 : out std_logic
-- );
--END component;
begin
process(clk)
begin
if clk'event and clk='1' then
if reset='1' then
shift_cnt0<="101";
else
case shift_cnt0 is
when "101"=>shift_cnt0<="000";
when others =>shift_cnt0<=shift_cnt0+"1";
end case;
end if;
shift_cnt0_temp0<=shift_cnt0;
shift_cnt0_temp1<=shift_cnt0_temp0;
shift_cnt0_temp2<=shift_cnt0_temp1;
shift_cnt0_temp3<=shift_cnt0_temp2;
shift_cnt0_temp4<=shift_cnt0_temp3;
shift_cnt0_temp5<=shift_cnt0_temp4;
shift_cnt0_temp6<=shift_cnt0_temp5;
shift_cnt0_temp7<=shift_cnt0_temp6;
shift_cnt0_temp8<=shift_cnt0_temp7;
--tcnt0<= shift_cnt0;--_temp4;
--tcnt0_t<= shift_cnt0_temp4;
end if;
end process;
process(clk)
begin
if clk'event and clk='1' then
case shift_cnt0 is
when "000" =>rbegin<='1';
when others=>rbegin<='0';
end case;
rbegin_temp0<=rbegin;
rbegin_temp1<=rbegin_temp0;
rbegin_temp2<=rbegin_temp1;
rbegin_temp3<=rbegin_temp2;
rbegin_temp4<=rbegin_temp3;
rbegin_temp5<=rbegin_temp4;
rbegin_temp6<=rbegin_temp5;
rbegin_temp7<=rbegin_temp6;
rbegin_temp8<=rbegin_temp7;
rbegin_temp9<=rbegin_temp8;
rbegin_temp10<=rbegin_temp9;
rbegin_temp11<=rbegin_temp10;
rbegin_temp12<=rbegin_temp11;
rbegin_temp13<=rbegin_temp12;
rbegin_temp14<=rbegin_temp13;
rbegin_temp15<=rbegin_temp14;
rbegin_temp16<=rbegin_temp15;
rbegin_temp17<=rbegin_temp16;
rbegin_temp18<=rbegin_temp17;
rbegin_temp19<=rbegin_temp18;
rbegin_temp20<=rbegin_temp19;
rbegin_temp21<=rbegin_temp20;
------------------------------------------
rbegin_temp22<=rbegin_temp21;
rbegin_temp23<=rbegin_temp22;
rbegin_temp24<=rbegin_temp23;
rbegin_temp25<=rbegin_temp24;
rbegin_temp26<=rbegin_temp25;
rbegin_temp27<=rbegin_temp26;
rbegin_temp28<=rbegin_temp27;
rbegin_temp29<=rbegin_temp28;
rbegin_temp30<=rbegin_temp29;
rbegin_temp31<=rbegin_temp30;
rbegin_temp32<=rbegin_temp31;
rbegin_temp33<=rbegin_temp32;
rbegin_temp34<=rbegin_temp33;
rbegin_temp35<=rbegin_temp34;
rbegin_temp36<=rbegin_temp35;
rbegin_temp37<=rbegin_temp36;
rbegin_temp38<=rbegin_temp37;
rbegin_temp39<=rbegin_temp38;
rbegin_temp40<=rbegin_temp39;
rbegin_temp41<=rbegin_temp40;
rbegin_temp42<=rbegin_temp41;
rbegin_temp43<=rbegin_temp42;
rbegin_temp44<=rbegin_temp43;
rbegin_temp45<=rbegin_temp44;
rbegin_temp46<=rbegin_temp45;
rbegin_temp47<=rbegin_temp46;
rbegin_temp48<=rbegin_temp47;
rbegin_temp49<=rbegin_temp48;
rbegin_temp50<=rbegin_temp49;
--t_rbegin<=rbegin;--_temp32;
--t_rbegin_t<=rbegin_temp3;--45;
end if;
end process;
process(clk)
begin
if clk'event and clk='1' then
case shift_cnt0 is
when "100" =>word_end<='1';
when others=>word_end<='0';
end case;
word_end_dly0<=word_end;
word_end_dly1<=word_end_dly0;
word_end_dly2<=word_end_dly1;
word_end_dly3<=word_end_dly2;
word_end_dly4<=word_end_dly3;
word_end_dly5<=word_end_dly4;
word_end_dly6<=word_end_dly5;
word_end_dly7<=word_end_dly6;
word_end_dly8<=word_end_dly7;
word_end_dly9<=word_end_dly8;
word_end_dly10<=word_end_dly9;
word_end_dly11<=word_end_dly10;
word_end_dly12<=word_end_dly11;
word_end_dly13<=word_end_dly12;
word_end_dly14<=word_end_dly13;
word_end_dly15<=word_end_dly14;
word_end_dly16<=word_end_dly15;
word_end_dly17<=word_end_dly16;
word_end_dly18<=word_end_dly17;
word_end_dly19<=word_end_dly18;
word_end_dly20<=word_end_dly19;
word_end_dly21<=word_end_dly20;
word_end_dly22<=word_end_dly21;
word_end_dly23<=word_end_dly22;
word_end_dly24<=word_end_dly23;
word_end_dly25<=word_end_dly24;
word_end_dly26<=word_end_dly25;
word_end_dly27<=word_end_dly26;
word_end_dly28<=word_end_dly27;
word_end_dly29<=word_end_dly28;
word_end_dly30<=word_end_dly29;
word_end_dly31<=word_end_dly30;
word_end_dly32<=word_end_dly31;
word_end_dly33<=word_end_dly32;
word_end_dly34<=word_end_dly33;
word_end_dly35<=word_end_dly34;
word_end_dly36<=word_end_dly35;
word_end_dly37<=word_end_dly36;
word_end_dly38<=word_end_dly37;
word_end_dly39<=word_end_dly38;
--word_end_dly40<=word_end_dly39;
--tword_end<=word_end;
--tword_end_dly<=word_end_dly0;
end if;
end process;
-------------------------------------------------------
process(clk)
begin
if clk'event and clk='1' then
da3<=mid_data(19 downto 15);
da2<=mid_data(14 downto 10);
da1<=mid_data(9 downto 5);
da0<=mid_data(4 downto 0);
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