📄 core32.vhd
字号:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
ENTITY core32 IS
PORT
(
--inclk : in std_logic;
clk : in std_logic;
reset : in std_logic;
pri_data : in std_logic_vector(19 downto 0);
mid_data : in std_logic_vector(19 downto 0);
itenum : in std_logic_vector(3 downto 0);
--flag : in std_logic;
--tcnt0 : out std_logic_vector(2 downto 0);
--tcnt0_t : out std_logic_vector(2 downto 0);
--tcnt1 : out std_logic_vector(2 downto 0);
--tda0,tda1,tda2,tda3 : out std_logic_vector(4 downto 0);---
--ab_d0,ab_d1,ab_d2,ab_d3 : out std_logic_vector(3 downto 0);---
--mi0,mi1,mi2,mi3 : out std_logic_vector(3 downto 0);---
--minum0,minum1,minum2,minum3 : out std_logic_vector(1 downto 0);---
--t_rbegin : out std_logic;
--t_rbegin_t : out std_logic;
--tm0,tm1,tm2,tm3 : out std_logic_vector(3 downto 0);
--tmcol0,tmcol1,tmcol2,tmcol3 : out std_logic_vector(2 downto 0);
--tmnum0,tmnum1,tmnum2,tmnum3 : out std_logic_vector(1 downto 0);
--hard_out : out std_logic_vector(3 downto 0);
--tword_end,tword_end_dly : out std_logic;
--tseq0,tseq1,tseq2,tseq3 : out std_logic_vector(3 downto 0);
--tseq4,tseq5,tseq6,tseq7 : out std_logic_vector(3 downto 0);
--tseq8,tseq9,tseqa,tseqb : out std_logic_vector(3 downto 0);
--tseqc,tseqd,tseqe,tseqf : out std_logic_vector(3 downto 0);
--hardo : out std_logic_vector(3 downto 0);
--tsyn0,tsyn1,tsyn2,tsyn3 : out std_logic_vector(4 downto 0);
--tsyn4,tsyn5,tsyn6,tsyn7 : out std_logic_vector(4 downto 0);
--tsyn8,tsyn9,tsyna,tsynb : out std_logic_vector(4 downto 0);
--tsync,tsynd,tsyne,tsynf : out std_logic_vector(4 downto 0);
--tpari0,tpari1,tpari2,tpari3 : out std_logic;
--tpari4,tpari5,tpari6,tpari7 : out std_logic;
--tpari8,tpari9,tparia,tparib : out std_logic;
--tparic,tparid,tparie,tparif : out std_logic;
--sv0,sv1,sv2,sv3 : out std_logic_vector(1 downto 0);
--sv4,sv5,sv6,sv7 : out std_logic_vector(1 downto 0);
--sv8,sv9,sva,svb : out std_logic_vector(1 downto 0);
--svc,svd,sve,svf : out std_logic_vector(1 downto 0);
--err_loc0,err_loc1,err_loc2,err_loc3 : out std_logic_vector(4 downto 0);
--err_loc4,err_loc5,err_loc6,err_loc7 : out std_logic_vector(4 downto 0);
--err_loc8,err_loc9,err_loca,err_locb : out std_logic_vector(4 downto 0);
--err_locc,err_locd,err_loce,err_locf : out std_logic_vector(4 downto 0);
--tseq_col : out std_logic_vector(3 downto 0);
--tcsq0,tcsq1,tcsq2,tcsq3,tcsq4 : out std_logic_vector(3 downto 0);
--tcsq5,tcsq6,tcsq7,tcsq8,tcsq9 : out std_logic_vector(3 downto 0);
--tcsqa,tcsqb,tcsqc,tcsqd,tcsqe : out std_logic_vector(3 downto 0);
--tcsqf : out std_logic_vector(3 downto 0);
--t_word_col : out std_logic_vector(2 downto 0);
--twd3,twd2,twd1,twd0 : out std_logic_vector(5 downto 0);
--wt0,wt1,wt2,wt3,wt4 : out std_logic_vector(9 downto 0);
--wt5,wt6,wt7,wt8,wt9 : out std_logic_vector(9 downto 0);
--wta,wtb,wtc,wtd,wte : out std_logic_vector(9 downto 0);
--wtf : out std_logic_vector(9 downto 0);
--tseqv : out std_logic_vector(15 downto 0);
--tmaxw0,tmaxonew0,tmaxzerow0 : out std_logic_vector(9 downto 0);
--tmaxnum0,tmaxonenum0,tmaxzeronum0 : out std_logic_vector(3 downto 0);
--tmaxv0,tmaxonev0,tmaxzerov0 : out std_logic;
--tmaxw1,tmaxonew1,tmaxzerow1 : out std_logic_vector(9 downto 0);
--tmaxnum1,tmaxonenum1,tmaxzeronum1 : out std_logic_vector(3 downto 0);
--tmaxv1,tmaxonev1,tmaxzerov1 : out std_logic;
--tmaxw2,tmaxonew2,tmaxzerow2 : out std_logic_vector(9 downto 0);
--tmaxnum2,tmaxonenum2,tmaxzeronum2 : out std_logic_vector(3 downto 0);
--tmaxv2,tmaxonev2,tmaxzerov2 : out std_logic;
--tmaxw3,tmaxonew3,tmaxzerow3 : out std_logic_vector(9 downto 0);
--tmaxnum3,tmaxonenum3,tmaxzeronum3 : out std_logic_vector(3 downto 0);
--tmaxv3,tmaxonev3,tmaxzerov3 : out std_logic;
--tmaxbit : out std_logic_vector(3 downto 0);
tdu0,tdu1,tdu2,tdu3 : out std_logic;--_vector(9 downto 0);
tde0,tde1,tde2,tde3 : out std_logic_vector(9 downto 0);
tpri : out std_logic_vector(19 downto 0);
--t_set : out std_logic;
--tse : out std_logic;
twe : out std_logic;
t_colad : out std_logic_vector(2 downto 0);
t_rowad : out std_logic_vector(5 downto 0)
--tp0,tp1,tp2,tp3 : out std_logic_vector(4 downto 0)
--iteration : out std_logic_vector(3 downto 0);
--outflag : out std_logic;
--saveflag : out std_logic
);
END entity;
ARCHITECTURE rtl OF core32 IS
--------------------------------------------------------------------------
signal shift_cnt0 : std_logic_vector(2 downto 0);
signal shift_cnt0_temp0,shift_cnt0_temp1,shift_cnt0_temp2 : std_logic_vector(2 downto 0);
signal shift_cnt0_temp3,shift_cnt0_temp4,shift_cnt0_temp5 : std_logic_vector(2 downto 0);
signal shift_cnt0_temp6,shift_cnt0_temp7,shift_cnt0_temp8 : std_logic_vector(2 downto 0);
signal cnt1 : std_logic_vector(2 downto 0);
signal abs_d0,abs_d1,abs_d2,abs_d3 : std_logic_vector(3 downto 0);
signal da0,da1,da2,da3 : std_logic_vector(4 downto 0);
signal rbegin : std_logic;
signal rbegin_temp0,rbegin_temp1,rbegin_temp2 : std_logic;
signal rbegin_temp3,rbegin_temp4,rbegin_temp5 : std_logic;
signal rbegin_temp6,rbegin_temp7,rbegin_temp8 : std_logic;
signal rbegin_temp9 : std_logic;
signal rbegin_temp10,rbegin_temp11,rbegin_temp12 : std_logic;
signal rbegin_temp13,rbegin_temp14,rbegin_temp15 : std_logic;
signal rbegin_temp16,rbegin_temp17,rbegin_temp18 : std_logic;
signal rbegin_temp19 : std_logic;
signal rbegin_temp20,rbegin_temp21,rbegin_temp22 : std_logic;
signal rbegin_temp23,rbegin_temp24,rbegin_temp25 : std_logic;
signal rbegin_temp26,rbegin_temp27,rbegin_temp28 : std_logic;
signal rbegin_temp29 : std_logic;
signal rbegin_temp30,rbegin_temp31,rbegin_temp32 : std_logic;
signal rbegin_temp33,rbegin_temp34,rbegin_temp35 : std_logic;
signal rbegin_temp36,rbegin_temp37,rbegin_temp38 : std_logic;
signal rbegin_temp39 : std_logic;
signal rbegin_temp40,rbegin_temp41,rbegin_temp42 : std_logic;
signal rbegin_temp43,rbegin_temp44,rbegin_temp45 : std_logic;
signal rbegin_temp46,rbegin_temp47,rbegin_temp48 : std_logic;
signal rbegin_temp49 : std_logic;
signal rbegin_temp50,rbegin_temp51,rbegin_temp52 : std_logic;
signal word_end : std_logic;
signal word_end_dly0,word_end_dly1,word_end_dly2 : std_logic;
signal word_end_dly3,word_end_dly4,word_end_dly5 : std_logic;
signal word_end_dly6,word_end_dly7,word_end_dly8 : std_logic;
signal word_end_dly9 : std_logic;
signal word_end_dly10,word_end_dly11,word_end_dly12 : std_logic;
signal word_end_dly13,word_end_dly14,word_end_dly15 : std_logic;
signal word_end_dly16,word_end_dly17,word_end_dly18 : std_logic;
signal word_end_dly19 : std_logic;
signal word_end_dly20,word_end_dly21,word_end_dly22 : std_logic;
signal word_end_dly23,word_end_dly24,word_end_dly25 : std_logic;
signal word_end_dly26,word_end_dly27,word_end_dly28 : std_logic;
signal word_end_dly29 : std_logic;
signal word_end_dly30,word_end_dly31,word_end_dly32 : std_logic;
signal word_end_dly33,word_end_dly34,word_end_dly35 : std_logic;
signal word_end_dly36,word_end_dly37,word_end_dly38 : std_logic;
signal word_end_dly39 : std_logic;
signal fa0,fa1,fa2,fa3 : std_logic_vector(3 downto 0);
signal fmi0,fmi1,fmi2,fmi3 : std_logic_vector(3 downto 0);
signal fminum0,fminum1,fminum2,fminum3 : std_logic_vector(1 downto 0);
signal hard,hard_shf0,hard_shf1,hard_shf2 : std_logic_vector(3 downto 0);
signal hard_shf3,hard_shf4,hard_shf5,hard_shf6 : std_logic_vector(3 downto 0);
signal hard_shf7,hard_shf8,hard_shf9,hard_shf10 : std_logic_vector(3 downto 0);
signal hard_shf11,hard_shf12,hard_shf13,hard_shf14 : std_logic_vector(3 downto 0);
signal hard_shf15,hard_shf16,hard_shf17,hard_shf18 : std_logic_vector(3 downto 0);
signal m0,m1,m2,m3 : std_logic_vector(3 downto 0);
signal mcol0,mcol1,mcol2,mcol3 : std_logic_vector(2 downto 0);
signal mnum0,mnum1,mnum2,mnum3 : std_logic_vector(1 downto 0);
signal gseq0,gseq1,gseq2,gseq3 : std_logic_vector(3 downto 0);
signal gseq4,gseq5,gseq6,gseq7 : std_logic_vector(3 downto 0);
signal gseq8,gseq9,gseqa,gseqb : std_logic_vector(3 downto 0);
signal gseqc,gseqd,gseqe,gseqf : std_logic_vector(3 downto 0);
signal syn0,syn1,syn2,syn3,syn4,syn5 : std_logic_vector(4 downto 0);
signal syn6,syn7,syn8,syn9,syna : std_logic_vector(4 downto 0);
signal synb,sync,synd,syne,synf : std_logic_vector(4 downto 0);
signal pari0,pari1,pari2,pari3,pari4,pari5 : std_logic;
signal pari6,pari7,pari8,pari9,paria : std_logic;
signal parib,paric,parid,parie,parif : std_logic;
signal errp0,errp1,errp2,errp3,errp4,errp5,errp6,errp7,errp8 : std_logic_vector(6 downto 0);
signal errp9,errpa,errpb,errpc,errpd,errpe,errpf : std_logic_vector(6 downto 0);
signal cor_sq0,cor_sq1,cor_sq2,cor_sq3 : std_logic_vector(3 downto 0);
signal cor_sq4,cor_sq5,cor_sq6,cor_sq7 : std_logic_vector(3 downto 0);
signal cor_sq8,cor_sq9,cor_sqa,cor_sqb : std_logic_vector(3 downto 0);
signal cor_sqc,cor_sqd,cor_sqe,cor_sqf : std_logic_vector(3 downto 0);
signal ptemp0,ptemp1,ptemp2,ptemp3 : std_logic;
signal ptemp4,ptemp5,ptemp6,ptemp7 : std_logic;
signal ptemp8,ptemp9,ptempa,ptempb : std_logic;
signal ptempc,ptempd,ptempe,ptempf : std_logic;
signal word_col : std_logic_vector(2 downto 0);
signal csq0,csq1,csq2,csq3,csq4 : std_logic_vector(3 downto 0);
signal csq5,csq6,csq7,csq8,csq9 : std_logic_vector(3 downto 0);
signal csqa,csqb,csqc,csqd,csqe : std_logic_vector(3 downto 0);
signal csqf : std_logic_vector(3 downto 0);
signal pri,pri_temp0,pri_temp1,pri_temp2,pri_temp3 : std_logic_vector(19 downto 0);
signal mid,mid_temp1,mid_temp2 : std_logic_vector(19 downto 0);
signal wd0,wd1,wd2,wd3 : std_logic_vector(5 downto 0);
signal dem : std_logic_vector(19 downto 0);
signal w0,w1,w2,w3,w4 : std_logic_vector(9 downto 0);
signal w5,w6,w7,w8,w9 : std_logic_vector(9 downto 0);
signal wa,wb,wc,wd,we : std_logic_vector(9 downto 0);
signal wf : std_logic_vector(9 downto 0);
signal validflag,seqv : std_logic_vector(15 downto 0);
signal wsq0,wsq1,wsq2,wsq3,wsq4 : std_logic_vector(3 downto 0);
signal wsq5,wsq6,wsq7,wsq8,wsq9 : std_logic_vector(3 downto 0);
signal wsqa,wsqb,wsqc,wsqd,wsqe : std_logic_vector(3 downto 0);
signal wsqf : std_logic_vector(3 downto 0);
--======================================================
signal maxw0,maxonew0,maxzerow0 : std_logic_vector(9 downto 0);
signal maxnum0,maxonenum0,maxzeronum0 : std_logic_vector(3 downto 0);
signal maxv0,maxonev0,maxzerov0 : std_logic;
signal maxw1,maxonew1,maxzerow1 : std_logic_vector(9 downto 0);
signal maxnum1,maxonenum1,maxzeronum1 : std_logic_vector(3 downto 0);
signal maxv1,maxonev1,maxzerov1 : std_logic;
signal maxw2,maxonew2,maxzerow2 : std_logic_vector(9 downto 0);
signal maxnum2,maxonenum2,maxzeronum2 : std_logic_vector(3 downto 0);
signal maxv2,maxonev2,maxzerov2 : std_logic;
signal maxw3,maxonew3,maxzerow3 : std_logic_vector(9 downto 0);
signal maxnum3,maxonenum3,maxzeronum3 : std_logic_vector(3 downto 0);
signal maxv3,maxonev3,maxzerov3 : std_logic;
signal lsq0,lsq1,lsq2,lsq3,lsq4 : std_logic_vector(3 downto 0);
signal lsq5,lsq6,lsq7,lsq8,lsq9 : std_logic_vector(3 downto 0);
signal lsqa,lsqb,lsqc,lsqd,lsqe : std_logic_vector(3 downto 0);
signal lsqf : std_logic_vector(3 downto 0);
signal maxbit : std_logic_vector(3 downto 0);
signal du0,de0,du1,de1,du2,de2,du3,de3 : std_logic_vector(9 downto 0);
signal reset_sft,rst0,rst1 : std_logic;
signal row_ad : std_logic_vector(5 downto 0);
signal col_ad0_temp0,col_ad0_temp1 : std_logic_vector(2 downto 0);
signal wetemp0 : std_logic;
--signal iteration_t0,iteration_t1 : std_logic_vector(3 downto 0);
component abs_of_data IS
PORT
(
clk : IN STD_LOGIC;
a0,a1,a2,a3 : in std_logic_vector(4 downto 0);
abs_a0,abs_a1,abs_a2,abs_a3 : out std_logic_vector(3 downto 0)
--abs_b0,abs_b1,abs_b2,abs_b3 : out std_logic_vector(4 downto 0)
);
END component;
component find_small IS
PORT
(
clk : IN STD_LOGIC;
a0,a1,a2,a3 : in std_logic_vector(3 downto 0);
set : in STD_LOGIC;
min0,min1,min2,min3 : out std_logic_vector(3 downto 0);
min0num,min1num,min2num,min3num : out std_logic_vector(1 downto 0)
);
END component;
component sort4 IS
PORT
(
clk : in std_logic;
set : in std_logic;
fa0,fa1,fa2,fa3 : in std_logic_vector(3 downto 0);
fa_col : in std_logic_vector(2 downto 0);
fa0_num,fa1_num,fa2_num,fa3_num : in std_logic_vector(1 downto 0);
Ls0,Ls1,Ls2,Ls3 : out std_logic_vector(3 downto 0);
Ls0_col,Ls1_col,Ls2_col,Ls3_col : out std_logic_vector(2 downto 0);
Ls0_num,Ls1_num,Ls2_num,Ls3_num : out std_logic_vector(1 downto 0)
);
END component;
component gen_tseq IS
PORT
(
clk : in std_logic;
lcol0,lcol1,lcol2,lcol3 : in std_logic_vector(2 downto 0);
lnum0,lnum1,lnum2,lnum3 : in std_logic_vector(1 downto 0);
hardin : in std_logic_vector(3 downto 0);
hcol : in std_logic_vector(2 downto 0);
seq0,seq1,seq2,seq3 : out std_logic_vector(3 downto 0);
seq4,seq5,seq6,seq7 : out std_logic_vector(3 downto 0);
seq8,seq9,seq10,seq11 : out std_logic_vector(3 downto 0);
seq12,seq13,seq14,seq15 : out std_logic_vector(3 downto 0)
);
END component;
component div IS
PORT
(
clk : in std_logic;
rowbegin : in std_logic;
rowend : in std_logic;
sq0,sq1,sq2,sq3,sq4,sq5 : in std_logic_vector(3 downto 0);
sq6,sq7,sq8,sq9,sq10 : in std_logic_vector(3 downto 0);
sq11,sq12,sq13,sq14,sq15 : in std_logic_vector(3 downto 0);
sy0,sy1,sy2,sy3,sy4,sy5 : out std_logic_vector(4 downto 0);
sy6,sy7,sy8,sy9,sy10 : out std_logic_vector(4 downto 0);
sy11,sy12,sy13,sy14,sy15 : out std_logic_vector(4 downto 0);
pr0,pr1,pr2,pr3,pr4,pr5 : out std_logic;
pr6,pr7,pr8,pr9,pr10 : out std_logic;
pr11,pr12,pr13,pr14,pr15 : out std_logic
);
END component;
component eptable IS
PORT
(
address : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (6 DOWNTO 0)
);
END component;
component shiftseq IS
PORT
(
clk : in std_logic;
indata : in std_logic_vector(3 downto 0);
outdata : out std_logic_vector(3 downto 0)
);
END component;
component shiftcnt1 IS
PORT
(
clk : in std_logic;
indata : in std_logic_vector(2 downto 0);
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -