abs_of_data.vhd

完整的TPC编译码VHDL程序

LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

ENTITY abs_of_data IS
	PORT
	(
		clk		                              : IN   STD_LOGIC;
		a0,a1,a2,a3                        : in   std_logic_vector(4 downto 0);
		abs_a0,abs_a1,abs_a2,abs_a3        : out  std_logic_vector(3 downto 0)
  --abs_b0,abs_b1,abs_b2,abs_b3        : out  std_logic_vector(4 downto 0)
	);
END entity;
----,a1,a2,a3
----,abs_a1,abs_a2,abs_a3
ARCHITECTURE rtl OF abs_of_data IS
signal d0,d1,d2,d3      : std_logic_vector(4 downto 0);


begin
----此时，默认0映射成-1，1映射成+1。
--------------------如果输入是补码。


process(clk)
begin
  if clk'event and clk='1' then
     if a0(4)='0' then
        abs_a0<= a0(3 downto 0);
     else 
        abs_a0<= not a0(3 downto 0);--+'1';  
     end if;

     if a1(4)='0' then
        abs_a1<= a1(3 downto 0);
     else 
        abs_a1<= not a1(3 downto 0);-- +'1';  
     end if;

     if a2(4)='0' then
        abs_a2<=a2(3 downto 0);
     else 
        abs_a2<=not a2(3 downto 0);--+'1';  
    end if;

     if a3(4)='0' then
        abs_a3<=a3(3 downto 0);
     else 
        abs_a3<=not a3(3 downto 0);--+'1';  
     end if;


  end if;
end process;

end rtl;