📄 max.vhd
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LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
ENTITY max IS
PORT
(
clk : in std_logic;
se0,se1,se2,se3,se4 : in std_logic;
se5,se6,se7,se8,se9 : in std_logic;
se10,se11,se12,se13,se14 : in std_logic;
se15 : in std_logic;
comw0,comw1,comw2,comw3,comw4 : in std_logic_vector(9 downto 0);
comw5,comw6,comw7,comw8,comw9 : in std_logic_vector(9 downto 0);
comw10,comw11,comw12,comw13,comw14 : in std_logic_vector(9 downto 0);
comw15 : in std_logic_vector(9 downto 0);
v : in std_logic_vector(15 downto 0);
maxw : out std_logic_vector(9 downto 0);
maxnum : out std_logic_vector(3 downto 0);
maxv : out std_logic;
maxonew : out std_logic_vector(9 downto 0);
maxonenum : out std_logic_vector(3 downto 0);
maxonev : out std_logic;
maxzerow : out std_logic_vector(9 downto 0);
maxzeronum : out std_logic_vector(3 downto 0);
maxzerov : out std_logic
);
END entity;
ARCHITECTURE rtl OF max IS
signal onev0,onev1,onev2,onev3,onev4 : std_logic;
signal onev5,onev6,onev7,onev8,onev9 : std_logic;
signal onev10,onev11,onev12,onev13,onev14 : std_logic;
signal onev15 : std_logic;
signal zerov0,zerov1,zerov2,zerov3,zerov4 : std_logic;
signal zerov5,zerov6,zerov7,zerov8,zerov9 : std_logic;
signal zerov10,zerov11,zerov12,zerov13,zerov14 : std_logic;
signal zerov15 : std_logic;
signal v0temp,v1temp,v2temp,v3temp,v4temp : std_logic;
signal v5temp,v6temp,v7temp,v8temp,v9temp : std_logic;
signal v10temp,v11temp,v12temp,v13temp,v14temp : std_logic;
signal v15temp : std_logic;
signal cw0,cw1,cw2,cw3,cw4 : std_logic_vector(9 downto 0);
signal cw5,cw6,cw7,cw8,cw9 : std_logic_vector(9 downto 0);
signal cw10,cw11,cw12,cw13,cw14 : std_logic_vector(9 downto 0);
signal cw15 : std_logic_vector(9 downto 0);
--===========================================================================
signal gw0_0,gw0_1,gw0_2,gw0_3,gw0_4 : std_logic_vector(9 downto 0);
signal gw0_5,gw0_6,gw0_7 : std_logic_vector(9 downto 0);
signal gn0_0,gn0_1,gn0_2,gn0_3,gn0_4 : std_logic_vector(3 downto 0);
signal gn0_5,gn0_6,gn0_7 : std_logic_vector(3 downto 0);
signal gv0_0,gv0_1,gv0_2,gv0_3,gv0_4 : std_logic;
signal gv0_5,gv0_6,gv0_7 : std_logic;
----------------------------
signal gw1_0,gw1_1,gw1_2,gw1_3,gw1_4 : std_logic_vector(9 downto 0);
signal gn1_0,gn1_1,gn1_2,gn1_3,gn1_4 : std_logic_vector(3 downto 0);
signal gv1_0,gv1_1,gv1_2,gv1_3,gv1_4 : std_logic;
----------------------------
signal gw2_0,gw2_1 : std_logic_vector(9 downto 0);
signal gn2_0,gn2_1 : std_logic_vector(3 downto 0);
signal gv2_0,gv2_1 : std_logic;
----------------------------
signal gw3_0 : std_logic_vector(9 downto 0);
signal gn3_0 : std_logic_vector(3 downto 0);
signal gv3_0 : std_logic;
----------------------------------------------------------------------------
signal gow0_0,gow0_1,gow0_2,gow0_3,gow0_4 : std_logic_vector(9 downto 0);
signal gow0_5,gow0_6,gow0_7 : std_logic_vector(9 downto 0);
signal gon0_0,gon0_1,gon0_2,gon0_3,gon0_4 : std_logic_vector(3 downto 0);
signal gon0_5,gon0_6,gon0_7 : std_logic_vector(3 downto 0);
signal gov0_0,gov0_1,gov0_2,gov0_3,gov0_4 : std_logic;
signal gov0_5,gov0_6,gov0_7 : std_logic;
------------------------------
signal gow1_0,gow1_1,gow1_2,gow1_3,gow1_4 : std_logic_vector(9 downto 0);
signal gon1_0,gon1_1,gon1_2,gon1_3,gon1_4 : std_logic_vector(3 downto 0);
signal gov1_0,gov1_1,gov1_2,gov1_3,gov1_4 : std_logic;
------------------------------
signal gow2_0,gow2_1 : std_logic_vector(9 downto 0);
signal gon2_0,gon2_1 : std_logic_vector(3 downto 0);
signal gov2_0,gov2_1 : std_logic;
------------------------------
signal gow3_0 : std_logic_vector(9 downto 0);
signal gon3_0 : std_logic_vector(3 downto 0);
signal gov3_0 : std_logic;
--------------------------------------------------------------------------------
signal gzw0_0,gzw0_1,gzw0_2,gzw0_3,gzw0_4 : std_logic_vector(9 downto 0);
signal gzw0_5,gzw0_6,gzw0_7 : std_logic_vector(9 downto 0);
signal gzn0_0,gzn0_1,gzn0_2,gzn0_3,gzn0_4 : std_logic_vector(3 downto 0);
signal gzn0_5,gzn0_6,gzn0_7 : std_logic_vector(3 downto 0);
signal gzv0_0,gzv0_1,gzv0_2,gzv0_3,gzv0_4 : std_logic;
signal gzv0_5,gzv0_6,gzv0_7 : std_logic;
--------------------------------
signal gzw1_0,gzw1_1,gzw1_2,gzw1_3,gzw1_4 : std_logic_vector(9 downto 0);
signal gzn1_0,gzn1_1,gzn1_2,gzn1_3,gzn1_4 : std_logic_vector(3 downto 0);
signal gzv1_0,gzv1_1,gzv1_2,gzv1_3,gzv1_4 : std_logic;
--------------------------------
signal gzw2_0,gzw2_1 : std_logic_vector(9 downto 0);
signal gzn2_0,gzn2_1 : std_logic_vector(3 downto 0);
signal gzv2_0,gzv2_1 : std_logic;
--------------------------------
signal gzw3_0 : std_logic_vector(9 downto 0);
signal gzn3_0 : std_logic_vector(3 downto 0);
signal gzv3_0 : std_logic;
-------------------------------------------------------------
component maxof2
PORT
(
clk : in std_logic;
coma : in std_logic_vector(9 downto 0);
comb : in std_logic_vector(9 downto 0);
anum,bnum : in std_logic_vector(3 downto 0);
va,vb : in std_logic;
lw : out std_logic_vector(9 downto 0);
lnum : out std_logic_vector(3 downto 0);
valid : out std_logic
);
END component;
begin
process(clk)
begin
if clk'event and clk='1' then
onev0<=se0 and v(0);
onev1<=se1 and v(1);
onev2<=se2 and v(2);
onev3<=se3 and v(3);
onev4<=se4 and v(4);
onev5<=se5 and v(5);
onev6<=se6 and v(6);
onev7<=se7 and v(7);
onev8<=se8 and v(8);
onev9<=se9 and v(9);
onev10<=se10 and v(10);
onev11<=se11 and v(11);
onev12<=se12 and v(12);
onev13<=se13 and v(13);
onev14<=se14 and v(14);
onev15<=se15 and v(15);
zerov0<=( not se0) and v(0);
zerov1<=( not se1) and v(1);
zerov2<=( not se2) and v(2);
zerov3<=( not se3) and v(3);
zerov4<=( not se4) and v(4);
zerov5<=( not se5) and v(5);
zerov6<=( not se6) and v(6);
zerov7<=( not se7) and v(7);
zerov8<=( not se8) and v(8);
zerov9<=( not se9) and v(9);
zerov10<=( not se10) and v(10);
zerov11<=( not se11) and v(11);
zerov12<=( not se12) and v(12);
zerov13<=( not se13) and v(13);
zerov14<=( not se14) and v(14);
zerov15<=( not se15) and v(15);
v0temp<=v(0);
v1temp<=v(1);
v2temp<=v(2);
v3temp<=v(3);
v4temp<=v(4);
v5temp<=v(5);
v6temp<=v(6);
v7temp<=v(7);
v8temp<=v(8);
v9temp<=v(9);
v10temp<=v(10);
v11temp<=v(11);
v12temp<=v(12);
v13temp<=v(13);
v14temp<=v(14);
v15temp<=v(15);
cw0<=comw0;
cw1<=comw1;
cw2<=comw2;
cw3<=comw3;
cw4<=comw4;
cw5<=comw5;
cw6<=comw6;
cw7<=comw7;
cw8<=comw8;
cw9<=comw9;
cw10<=comw10;
cw11<=comw11;
cw12<=comw12;
cw13<=comw13;
cw14<=comw14;
cw15<=comw15;
end if;
end process;
------------------------------------------------------
max0_0: maxof2 port map(clk,cw0,cw1,"0000","0001",v0temp,v1temp,gw0_0,gn0_0,gv0_0);
max0_1: maxof2 port map(clk,cw2,cw3,"0010","0011",v2temp,v3temp,gw0_1,gn0_1,gv0_1);
max0_2: maxof2 port map(clk,cw4,cw5,"0100","0101",v4temp,v5temp,gw0_2,gn0_2,gv0_2);
max0_3: maxof2 port map(clk,cw6,cw7,"0110","0111",v6temp,v7temp,gw0_3,gn0_3,gv0_3);
max0_4: maxof2 port map(clk,cw8,cw9,"1000","1001",v8temp,v9temp,gw0_4,gn0_4,gv0_4);
max0_5: maxof2 port map(clk,cw10,cw11,"1010","1011",v10temp,v11temp,gw0_5,gn0_5,gv0_5);
max0_6: maxof2 port map(clk,cw12,cw13,"1100","1101",v12temp,v13temp,gw0_6,gn0_6,gv0_6);
max0_7: maxof2 port map(clk,cw14,cw15,"1110","1111",v14temp,v15temp,gw0_7,gn0_7,gv0_7);
max1_0: maxof2 port map(clk,gw0_0,gw0_1,gn0_0,gn0_1,gv0_0,gv0_1,gw1_0,gn1_0,gv1_0);
max1_1: maxof2 port map(clk,gw0_2,gw0_3,gn0_2,gn0_3,gv0_2,gv0_3,gw1_1,gn1_1,gv1_1);
max1_2: maxof2 port map(clk,gw0_4,gw0_5,gn0_4,gn0_5,gv0_4,gv0_5,gw1_2,gn1_2,gv1_2);
max1_3: maxof2 port map(clk,gw0_6,gw0_7,gn0_6,gn0_7,gv0_6,gv0_7,gw1_3,gn1_3,gv1_3);
max2_0: maxof2 port map(clk,gw1_0,gw1_1,gn1_0,gn1_1,gv1_0,gv1_1,gw2_0,gn2_0,gv2_0);
max2_1: maxof2 port map(clk,gw1_2,gw1_3,gn1_2,gn1_3,gv1_2,gv1_3,gw2_1,gn2_1,gv2_1);
max3_0: maxof2 port map(clk,gw2_0,gw2_1,gn2_0,gn2_1,gv2_0,gv2_1,gw3_0,gn3_0,gv3_0);
-------------------------------------------------
maxone0_0: maxof2 port map(clk,cw0,cw1,"0000","0001",onev0,onev1,gow0_0,gon0_0,gov0_0);
maxone0_1: maxof2 port map(clk,cw2,cw3,"0010","0011",onev2,onev3,gow0_1,gon0_1,gov0_1);
maxone0_2: maxof2 port map(clk,cw4,cw5,"0100","0101",onev4,onev5,gow0_2,gon0_2,gov0_2);
maxone0_3: maxof2 port map(clk,cw6,cw7,"0110","0111",onev6,onev7,gow0_3,gon0_3,gov0_3);
maxone0_4: maxof2 port map(clk,cw8,cw9,"1000","1001",onev8,onev9,gow0_4,gon0_4,gov0_4);
maxone0_5: maxof2 port map(clk,cw10,cw11,"1010","1011",onev10,onev11,gow0_5,gon0_5,gov0_5);
maxone0_6: maxof2 port map(clk,cw12,cw13,"1100","1101",onev12,onev13,gow0_6,gon0_6,gov0_6);
maxone0_7: maxof2 port map(clk,cw14,cw15,"1110","1111",onev14,onev15,gow0_7,gon0_7,gov0_7);
maxone1_0: maxof2 port map(clk,gow0_0,gow0_1,gon0_0,gon0_1,gov0_0,gov0_1,gow1_0,gon1_0,gov1_0);
maxone1_1: maxof2 port map(clk,gow0_2,gow0_3,gon0_2,gon0_3,gov0_2,gov0_3,gow1_1,gon1_1,gov1_1);
maxone1_2: maxof2 port map(clk,gow0_4,gow0_5,gon0_4,gon0_5,gov0_4,gov0_5,gow1_2,gon1_2,gov1_2);
maxone1_3: maxof2 port map(clk,gow0_6,gow0_7,gon0_6,gon0_7,gov0_6,gov0_7,gow1_3,gon1_3,gov1_3);
maxone2_0: maxof2 port map(clk,gow1_0,gow1_1,gon1_0,gon1_1,gov1_0,gov1_1,gow2_0,gon2_0,gov2_0);
maxone2_1: maxof2 port map(clk,gow1_2,gow1_3,gon1_2,gon1_3,gov1_2,gov1_3,gow2_1,gon2_1,gov2_1);
maxone3_0: maxof2 port map(clk,gow2_0,gow2_1,gon2_0,gon2_1,gov2_0,gov2_1,gow3_0,gon3_0,gov3_0);
-----------------------------------------------------------------------------------
maxzero0_0: maxof2 port map(clk,cw0,cw1,"0000","0001",zerov0,zerov1,gzw0_0,gzn0_0,gzv0_0);
maxzero0_1: maxof2 port map(clk,cw2,cw3,"0010","0011",zerov2,zerov3,gzw0_1,gzn0_1,gzv0_1);
maxzero0_2: maxof2 port map(clk,cw4,cw5,"0100","0101",zerov4,zerov5,gzw0_2,gzn0_2,gzv0_2);
maxzero0_3: maxof2 port map(clk,cw6,cw7,"0110","0111",zerov6,zerov7,gzw0_3,gzn0_3,gzv0_3);
maxzero0_4: maxof2 port map(clk,cw8,cw9,"1000","1001",zerov8,zerov9,gzw0_4,gzn0_4,gzv0_4);
maxzero0_5: maxof2 port map(clk,cw10,cw11,"1010","1011",zerov10,zerov11,gzw0_5,gzn0_5,gzv0_5);
maxzero0_6: maxof2 port map(clk,cw12,cw13,"1100","1101",zerov12,zerov13,gzw0_6,gzn0_6,gzv0_6);
maxzero0_7: maxof2 port map(clk,cw14,cw15,"1110","1111",zerov14,zerov15,gzw0_7,gzn0_7,gzv0_7);
maxzero1_0: maxof2 port map(clk,gzw0_0,gzw0_1,gzn0_0,gzn0_1,gzv0_0,gzv0_1,gzw1_0,gzn1_0,gzv1_0);
maxzero1_1: maxof2 port map(clk,gzw0_2,gzw0_3,gzn0_2,gzn0_3,gzv0_2,gzv0_3,gzw1_1,gzn1_1,gzv1_1);
maxzero1_2: maxof2 port map(clk,gzw0_4,gzw0_5,gzn0_4,gzn0_5,gzv0_4,gzv0_5,gzw1_2,gzn1_2,gzv1_2);
maxzero1_3: maxof2 port map(clk,gzw0_6,gzw0_7,gzn0_6,gzn0_7,gzv0_6,gzv0_7,gzw1_3,gzn1_3,gzv1_3);
maxzero2_0: maxof2 port map(clk,gzw1_0,gzw1_1,gzn1_0,gzn1_1,gzv1_0,gzv1_1,gzw2_0,gzn2_0,gzv2_0);
maxzero2_1: maxof2 port map(clk,gzw1_2,gzw1_3,gzn1_2,gzn1_3,gzv1_2,gzv1_3,gzw2_1,gzn2_1,gzv2_1);
maxzero3_0: maxof2 port map(clk,gzw2_0,gzw2_1,gzn2_0,gzn2_1,gzv2_0,gzv2_1,gzw3_0,gzn3_0,gzv3_0);
----------------------------------------------------------------------------------------------
process(clk)
begin
if clk'event and clk='1' then
maxw<=gw3_0;
maxnum<=gn3_0;
maxv<=gv3_0;
maxonew<=gow3_0;
maxonenum<=gon3_0;
maxonev<=gov3_0;
maxzerow<=gzw3_0;
maxzeronum<=gzn3_0;
maxzerov<=gzv3_0;
end if;
end process;
end rtl;⌨️ 快捷键说明
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